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參數(shù)資料
| 型號： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數(shù)： | 24/145頁 |
| 文件大小： | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
12
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
P_PERR#
I
VDD3.3
Parity Error. P_PERR# is used for reporting data parity errors during all PCI
transactions except a special cycle. An external PCI device drives PERR#
when it receives data that has a parity error. The I/O Controller can either
generate a NMI# or SMI# upon detecting a parity error.
P_REQ_1#
0
VDD3.3
PCI Request 1. An active low assertion indicates that the I/O Controller
desires use of the PCI bus. Primary arbitration request
P_REQ_2#
O
VDD3.3
PCI Request 2. Optional dedicated PCI request for internal IDE and USB,
with P_REQ_1# dedicated to the LPC bridge. Secondary arbitration request
P_REQ#
[4:0]
IVDD3.3
PCI Request. P_REQ#[4:0] signals are used by PCI devices to request access
to the PCI bus. The power management unit monitors these inputs with
the internal PCI masters in order to wake the CPU in the case of master
attempting a bus master cycle while the CPU is in a Sleep state.
P_SERR#
I
VDD3.3
PCI System Error. P_SERR# is used for reporting address parity errors, data
parity errors on the special cycle command, or any other system error
where the result will be catastrophic. P_SERR# can be pulsed active by any
PCI device that detects a system error condition. Upon sampling SERR#
active, the I/O Controller has the ability to generate a NMI#, SMI#, or SCI
interrupt.
P_STOP#
I/O
VDD3.3
PCI Stop. P_STOP# indicates that the I/O Controller, as a target, is request-
ing the initiator to stop the current transaction. P_STOP# causes the I/O
Controller, as an initiator, to stop the current transaction. P_STOP# is an
output when the I/O Controller is a target and an input when the I/O Con-
troller is an initiator.
P_TRDY#
I/O
VDD3.3
PCI Target Ready. Output when the I/O controller functions as a target and
input when I/O controller functions as the initiator.
PCI Signal Descriptions (continued)
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
USB Interface
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
USB_DATA1P
USB_DATA1N
USB I/O
Standby
USB Port 1. Differential signals used to transmit USB data, address, and
command. Supports both full speed (12Mb) and low speed (1.5Mb) data
rates. Powered off of the standby plane.
USB_DATA2P
USB_DATA2N
USB I/O
Standby
USB Port 2. Differential signals used to transmit USB data, address, and
command. Supports both full speed (12Mb) and low speed (1.5Mb) data
rates. Powered off of the standby plane.
USB_DATA3P
USB_DATA3N
USB I/O
Standby
USB Port 3. Differential signals used to transmit USB data, address, and
command. Supports both full speed (12Mb) and low speed (1.5Mb) data
rates. Powered off of the standby plane.
USB_DATA4P
USB_DATA4N
USB I/O
Standby
USB Port 4. Differential signals used to transmit USB data, address, and
command. Supports both full speed (12Mb) and low speed (1.5Mb) data
rates. Powered off of the standby plane.
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