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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 35/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
13
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
USB_OVRCUR
I
VDD3.3
Over-current Indicators signals set corresponding bits in the USB control-
lers to indicate that an over-current condition has occurred.
USB_PWR_EN
I/O
VDD3.3
USB Power Control.
USB Interface
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
SMBus Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
ALERT/
GPIO[14]
I
Standby
SMBus Alert. ALERT is used to generate an SMI or SCI interrupt associ-
ated with the SMBus logic. ALERT# is sampled at the rising edge of the
PCLK. ALERT# is used to inform the S/W that a SMB device wishes to be
serviced. When the ALERT# is being serviced, software needs to gener-
ate an ARA (Alert Response Address) transfer to determine which device
needs servicing, see SMB spec. 1.1 for details. Sometimes used as the
Super-IO PME. Optional GPIO.
SMB_CLK/
GPIO[16]
I/O
Standby
SMBus Clock. SMB_CLK is the system management bus (SMBus) clock.
Optional GPIO.
SMB_DATA/
GPIO[15]
I/O
Standby
SMBus Data. SMB_DATA is the system management bus (SMBus) data.
Optional GPIO.
LPC Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
L_AD[3:0]
I/O
VDD3.3
L_AD[3:0] signals contain the multiplexed address, command, and data.
L_DRQ[1:0]
I
VDD3.3
Encoded DMA/Bus Master Request signals are used by LPC devices to
request a DMA or bus master cycle.
L_FRAME#
O
VDD3.3
LPC Frame is used by the I/O Controller to initiate the start of a new LPC
cycle or to terminate a broken cycle. L_FRAME# require a weak external
pull-up.
L_SERIRQ
I/O
VDD3.3
Serial Interrupt Request is used to provide serialized IRQ support to LPC
devices.
APIC Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
APIC_CLK
I
9DD APIC Clock.The APIC clock can run at any speed up to 33 MHz.
APIC_D[1]/GPIO[18]
APIC_D[0]/GPIO[17]
I/O
9DD
These bi-directional open drain signals are used to send and receive
data over the APIC bus. As inputs, the data is valid on the rising edge
of APIC_CLK. As outputs, new data is driven from the rising edge of
the APIC_CLK.Optional GPIO.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
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| MT8LSDT1664AG-10EB1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1GBIT 168UDIMM - Trays |
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