參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 46/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
14
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
APIC_FLUSH_ACK
I
9DD
APIC Flush Acknowledge. Connected to the Host Controller APIC Flush
Request pin to acknowledge that write buffers are flushed to memory.
APIC_FLUSH_REQ
O
9DD
APIC Flush Request. Connected to the Host Controller APIC Flush
Request pin to request that write buffers must be flushed to
memory.
APIC Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
IDE
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
IDE_PRI_D [15:0]
IDE_SEC_D [15:0]
I/O
VDD3.3
The Primary and Secondary IDE channels each have a 16-bit data path.
These signals connect to the corresponding signals on the IDE
connector.
IDE_PRI_IORD#
IDE_SEC_IORD#
OVDD3.3
Primary and Secondary I/O Read signals are used in different ways
depending on the mode and type of transfer. For PIO and Non-Ultra
DMA transfers these signals inform the IDE device that it may drive
data onto the primary or secondary IDE data lines. The I/O Controller
latches the data on the deassertion (rising) edge of IDE_PRI_IORD# or
IDE_SEC_IORD#. The IDE device is selected by the ATA chip selects or
the IDE DMA acknowledge. For Ultra DMA writes to disk these signals
are the data write strobes. When writing to the disk I/O Controller
drives valid data onto the bus on rising and falling edges of
IDE_PRI_IORD#, IDE_SEC_IORD#. For Ultra DMA reads form the disk
these signals indicate DMA ready. When reading from the disk I/O Con-
troller will deassert IDE_PRI_IORD#, IDE_SEC_IORD# to pause burst data
transfers.
IDE_PRI_IOCHRDY
IDE_SEC_IOCHRDY
IVDD3.3
Primary and Secondary I/O channel ready signals are used in different
ways depending on the mode and type of transfer. For PIO mode trans-
fers these signals are used to add wait states to a transfer. For Ultra
DMA reads from the disk I/O Controller latches data on the rising and
falling edges of these signals. For Ultra DMA writes to disk these sig-
nals are used by the IDE device to pause burst data transfers.
IDE_PRI_DACK#
IDE_SEI_DACK#
OVDD3.3
Primary and Secondary IDE Device DMA Acknowledge signals are
driven by the I/O Controller when it is ready to fill a previous request
on IDE_PRI_DRQ or IDE_SEC_DRQ from the IDE device.
IDE_PRI_DRQ
IDE_SEC_DRQ
IVDD3.3
Primary and Secondary IDE Device DMA Request signals are driven by
the IDE device to request the transfer of DMA data.
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