參數(shù)資料
型號: MT90221
廠商: Mitel Networks Corporation
英文描述: Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備(四端口ATM IMA和UNI處理器))
中文描述: 四IMA的/單向物理層設(shè)備(IMA的四端口/單向物理層設(shè)備(四端口自動柜員機(jī)IMA的和單向處理器))
文件頁數(shù): 71/116頁
文件大小: 309K
代理商: MT90221
MT90221
63
Address (Hex):
Direct access
286
This register contains the link number associated with the RX Delay value
Register.
00
Reset Value (Hex):
Bit #
Type
Description
7:2
1:0
R/W
R/W
Reserved, write 000100 to these bits for normal operation.
Number of the physical link associated with the value in the RX Delay register. This value
is not valid when reading the Maximum Delay over time value is read.
Table 70 - RX Delay Link Number Register
Address (Hex):
Direct access
in number of cells)
Reset Value (Hex):
288, 28A, 28C, 28E
1 value for each IMA Group to use for start-up and adding/removing delay (value
04
Bit #
Type
Description
7:0
R/W
LSB of the Guardband/Delay value Bits 7:0.
Table 71 - RX Guardband/Delta Delay LSB Register
Address (Hex):
Direct access
287, 289, 28B, 28D
1 value for each IMA Group to use for start-up and adding/removing delay
(value in number of cells)
00
Reset Value (Hex):
Bit #
Type
Description
7:6
5:0
R/W
R/W
Unused. Read 0 after reset.
MSB of the Guardband/Delay value Bits 13:8.
Table 72 - RX Guardband/Delta Delay MSB Register
Address (Hex):
Direct access
Reset Value (Hex):
296, 298, 29A, 29C
1 register per IMA Group (value in number of cells)
00
Bit #
Type
Description
7:0
R/W
LSB of the Maximum Operational Delay value Bits 7:0.
Table 73 - RX Maximum Operational Delay LSB Register
Address (Hex):
Direct access
Reset Value (Hex):
295, 297, 299, 29B
1 reg. per IMA Group (value in number of cells)
00
Bit #
Type
Description
7:6
5:0
R/W
R/W
Unused. Read 0 after reset.
MSB of the Maximum Operational Delay value Bits 13:8.
Table 74 - RX Maximum Operational Delay MSB Register
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