參數(shù)資料
型號： MT9076AB
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 3.3V Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器
文件頁數(shù)： 110/160頁
文件大?。?/td> 416K
代理商： MT9076AB
MT9076
Preliminary Information
106
Bit
Name
Functional Description
7 - 6
- -
Reserved.
Must be kept at 0 for normal operation.
5
IMA
Inverse Mux Mode.
Setting this bit high the I/O ports to allow for easy connection to the
Mitel MT90220. DSTi becomes a serial 2.048 data stream. C4b becomes a 2.048 MHz clock
that clocks DSTi in on the falling edge. RXFP becomes a positive framing pulse that is high
for the first bit of the serial E1 stream coming from the pin DSTo. The data from DSTo is
clocked out on the rising edge of Exclk. Set this pin low for all other applications.
4 - 3
- -
Reserved.
Must be kept at 0 for normal operation.
2
8Men
8Mb/s Bit Rate Select.
Setting this bit low enables a serial bit rate on DSTi, CSTi and
DSTo,CSTo of 2.048 Mb/s. Setting this bit high enables a gapped serial bit rate of 8.192 Mb/
s on DSTi, CSTi, DSTo and CSTo.
1 - 0
8MTS1- 0
8 Mb/s Time Slot Select.
These two bits select the active timeslots on the serial 8.192 Mb/s
channels. During the active timeslots incoming serial data on DSTi and CSTi is clocked into
the device, and data is clocked out onto DSTo and CSTo. During inactive timeslots DSTo
and CSTo are tristate. For all selections every fourth 8 Mb/s timeslot is active.
The timeslot selection is as follows:
8MTS1 8MST0 Active timeslots
0
0 0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92
96,100,104,108,112,116,120,124
0
1 1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61,65,69,73,77,81,85,89,93
97,101,105,109,113,117,121,125
1
0
2 ,6,10,14,18,22,26,30,34,38,42,46,50,54,58,62,66,70,74,78,82,86,
90, 94, 98,102,106,110,114,118,122,126
1
1 3,7,11,15,19,23,27,31,35,39,43,47,51,55,59,63,67,71,75,79,83,87,91,95
99,103,107,111,115,119,123,127
Table 109 - Serial Bit Rate
(Page 2, Address 18H) (E1)
Bit
Name
Functional Description
7
En
Enable.
Set high to attach the HDLC0 controller to the channel specified below. Set
low to disconnect the HDLC0.
6
SaSEL
Sa Bits Select.
Set this bit to 0 to attach HDLC0 to the Sa bits. Set this bit to 1 to
attach HDLC0 to a payload timeslot.
5
- -
Reserved.
Must be kept at 0 for normal operation.
4-0
CH4-0
Channel 4-0.
This 5 bit number specifies the channel time HDLC0 will be attached
to if enabled. Channel 0 is the first channel in the frame. Channel 31 is the last
channel in an E1 frame. If enabled in a channel, HDLC data will be substituted for
data from DSTi on the transmit side. Receive data is extracted from the incoming
line data before the elastic buffer.
Table 110 - HDLC0 Select
(Page 2, Address 19H) (E1)
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
MT9076AP 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver
MT9076B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
MT9076BB 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BB1 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
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