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參數(shù)資料
| 型號： | MT90810 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
| 中文描述： | 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路） |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 176K |
| 代理商： | MT90810 |
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MT90810
Preliminary Information
2-182
Name
Description
Mode [bits]
Function
SEL_S8K
Selects source of 8kHz signal driven out on SEC8K pin
0 [00]
Select EX_8KA as SEC8K output
1 [01]
Select EX_8KB as SEC8K output
2 [10]
Select FRAME as SEC8K output
3 [11]
RESERVED
Enables SEC8K as output
Table 8 - EN_SEC8K and SEL_S8K bits
EN_SEC8K
Mode
[bits]
Description
APLL source
Frame Sync.
Function
0 [000]
X1 divided by
1,2, or 4
no frame
sync.
FMIC as Timing Master
FMIC defaults to this mode after reset (Clock Control Register
is cleared).
X1 divided by 1,2 or 4 is used as the input to the APLL.
State machine is free running and does not synchronize to any
external 8kHz source.
XCLK_SEL can be programmed to any mode.
MVIP_MST bit in MCS is set.
Used when the FMIC is to become the timing master in a
system which has no digital network connections (T1 or E1).
FMIC as MVIP Master
(Slaved to external 8kHz)
DPLL is selected as the source to the APLL. Input to the DPLL
is either SEC8K,EX8KA/EX8KB.
State machine is not synchronized to external 8kHz (SEC8K/
EX8KA/B); that is, FRAME signal is freq locked but not
necessarily phase aligned with external 8kHz.
XCLK_SEL must be programmed to mode 0.
MVIP_MST bit in MCS is set.
FMIC as MVIP Slave
FMIC is entirely slaved to MVIP bus timing.
MVIP C4 is selected as input to APLL.
State machine is synchronized to MVIP C4 and F0 inputs.
MVIP_MST bit in MCS register must be cleared.
FMIC as MVIP Master
(Slaved to external 8kHz)
DPLL is selected as the source to the APLL. Input to the DPLL
is either SEC8K,EX8KA/EX8KB.
State machine is synchronized to external 8kHz (SEC8K/
EX8KA/B); that is, FRAME signal is freq locked and phase
aligned with external 8kHz.
XCLK_SEL must be programmed to mode 0.
MVIP_MST bit in MCS must be set.
Table 9 - PLL_MODE bits (control PLL and frame synchronization)
1 [001]
2 [010]
3 [011]
SEC8K >DPLL
EX8KA >DPLL
EX8KB >DPLL
no frame
sync.
4 [100]
MVIP C4
frame sync.
to F0
5 [101]
SEC8K >DPLL
frame sync.
to SEC8K
frame sync.
to EX8KA
frame sync.
to EX_8KB
6 [110]
EX8KA >DPLL
7 [111]
EX8KB >DPLL
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