參數(shù)資料
型號(hào)： MT90810
廠商： Mitel Networks Corporation
英文描述： Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路)
中文描述： 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路）
文件頁(yè)數(shù)： 21/33頁(yè)
文件大?。?/td> 176K
代理商： MT90810
Preliminary Information
MT90810
2-189
JTAG Support
The FMIC JTAG interface is designed to the
Boundary-Scan standard IEEE1149.1. The standard
specifies a design-for-testability technique called
Boundary-Scan Test (BST). A boundary-scan IC has
a shift-register stage or ‘Boundary-Scan Cell’ (BSC)
in between the core logic and the I/O buffers
adjacent to each I/O pin. The BSCs can control and
observe what happens at each I/O pin of the IC. The
operation of the boundary-scan circuitry is controlled
by a Test Access Port (TAP) Controller.
Figure 12 - A Typical Boundary-Scan IC
Test Access Port (TAP)
The Test Access Port (TAP) provides access to many
test support functions built into the FMIC. It consists
of three input connections and one output
connection. The following connections form the TAP:
Test Clock Input (TCK)
TCK provides the clock for the test logic. The
TCK must not interfere with any on-chip clock
and thus remain independent. This permits
shifting of test data into or out of the
Boundary-Scan register cells concurrently with
the operation of the device without interfering
with on-chip logic.
Test Mode Select Input (TMS)
The logic signal (0’s and 1’s) received at the
TMS input are interpreted by the TAP Controller
to control the test operations. The TMS signals
are sampled at the rising edge of the TCK
pulses. When TMS is not driven from an
external source, the test logic perceives a logic
1.
The Test Data Input (TDI)
Serial input data applied to this port is fed
either into the instruction register or into a test
data register, depending on the sequence
previously applied to the TMS input. Both
CORE LOGIC
T
A
P
C
O
N
T
R
O
L
L
E
R
TEST DATA IN (TDI)
TEST DATA OUT (TDO)
TEST CLOCK (TCK)
TEST MODE
SELECT (TMS)
BOUNDARY -SCAN CELL(BSC)
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
I[0:1] Instruction
Description
[00] EXTEST
Boundary-Scan
register selected,
Test Enabled
This instruction is specifically provided to allow board-level interconnect
testing of opens, bridging errors etc.
When the EXTEST instruction is selected, the on-chip logic is isolated
from the FMIC’s I/O pin such that the value of the I/O pins is determined
by its boundary-scan register. Data for the execution of this instruction
can be preloaded into the boundary-scan register with the SAMPLE/
PRELOAD instruction.
Two functions can be performed by the use of this instruction. It allows a
SAMPLE (‘snapshot’) of the normal operation of the FMIC to be taken for
examination. And, prior to the selection of another test operation, a
PRELOAD can place data values into the latched parallel outputs of the
Boundary-Scan cells. During the execution of the instruction, the on-chip
logic operation is not hampered in any way.
This instruction is used to BYPASS the FMIC while sampling or loading
the data registers in other devices with scan registers in the same serial
register chain. The FMIC is in test mode and the value of it’s I/O pins is
determined by its boundary-scan register.
This instruction is used to BYPASS the FMIC while performing
boundary-scan testing on other devices with scan registers in the same
serial register chain. The FMIC is allowed to function normally. This
instruction is automatically loaded upon reset of the FMIC, as specified
in IEEE1149.1
Table 23 - Instruction Register
[01] SAMPLE/
PRELOAD
Boundary-Scan
register selected,
Test Disabled
[10] BYPASS/
TEST
Bypass register
selected,
Test Enabled
[11] BYPASS/
NOTEST
Bypass register
selected,
Test Disabled
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