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參數(shù)資料
| 型號： | MT90810 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
| 中文描述： | 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路） |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 176K |
| 代理商： | MT90810 |
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MT90810
Preliminary Information
2-174
Figure 3 - Per-channel Direction Control
0
1
2
3
30
29
31
. . . . .
FMIC
DC=0 for stream 0 channel 1
DSi0
DC=1 for stream 0 channel 29
I/P
O/P
I/P
O/P
DSo0
0
1
2
3
30
29
31
. . . . .
necessary to first write the low bits and then the high
bits. The low bits are held in a temporary register
until the high bits are written. The complete write of
all 12 bits (to connection memory) is only performed
when the high bits are being written.
Connection and Message Modes
In connection mode, the connection memory low
byte and the least significant bit of connection
memory high form a 9 bit address to point to in data
memory. The location pointed to specifies which
source/input channel to connect to the respective
output channel and stream. The same source
channel can be routed to various output channels,
thus providing broadcast facility within the switch.
In message mode, the connection memory low byte
is sent directly out the corresponding output channel
and stream. The least significant bit of connection
memory high is not used.
Direction Control Bit
The direction control (DC) bit in connection memory
high determines the direction of the associated
DSi-DSo channel pair. If the DSi or DSo channel is
programmed as an input, the corresponding DSo or
DSi channel will automatically be configured as an
output. Thus, there are always 256 MVIP input and
256 MVIP output channels or 256 full duplex MVIP
channels on the MVIP bus. Figure 3 - “Per channel
direction control” illustrates the use of DC bit for
direction control on stream 0 channel 1 and channel
29. When DC bit is set, DSo channel is output from
the FMIC and DSi is input to the FMIC. When DC bit
is cleared, the channel directions are reversed.
Timing and Clock Control
The FMIC clock control circuitry contains an on-chip
analog PLL (with external loop filter) which is
designed to phase lock to a 4.096MHz clock. The
on-chip VCO runs at eight times this rate yielding a
32MHz clock which is divided by two. The resulting
16.384MHz is used as the internal master clock of
the FMIC.
The input to the analog PLL can be selected from
among several different sources including, the MVIP
C4 clock which is used as the internal master clock
of the FMIC.
The on-chip digital PLL generates a 4.096MHz clock
which is phase locked to an externally generated
8kHz clock. The digital PLL state machine is clocked
at 16.384MHz. The digital PLL maintains lock by
occasionally dropping or repeating a 16.384MHz
clock period on the generated 4.096MHz clock.
Consequently, the 4.096MHz clock has jitter equal to
about 60ns. If the output of the digital PLL is chosen
as the input to the analog PLL, a slow loop filter with
a time constant greater than several 8kHz frames will
smooth out the jitter.
The clock oscillator pins X1 and X2 can be used with
an external 16.384MHz crystal or pin X1 can be used
directly as a clock input with X2 left unconnected.
When X1 is used as a clock input, the frequency of
the clock can be selected to be either 16.384MHz or
8.192MHz or 4.096MHz by changing the XCLK_SEL
bits in the CLK_CNTL register.
The overall FMIC state machine from which all timing
is derived, is clocked by the 16.384MHz output of the
analog PLL, the device’s master clock. The state
machine controls all timing in the FMIC and has a
period equal to one MVIP frame (8kHz). This state
machine can either free run or synchronize to an
8kHz source such as the MVIP F0 signal or an
external 8kHz reference.
Refer to Figure 4 - “Clock Control Functional Block
Diagram” for further details.
The operation of the PLLs and the state machine is
controlled by the clock control register as described
in Figure 6 - “Clock Control (CLK_CNTRL) Register”
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