參數(shù)資料
型號： MT90810
廠商： Mitel Networks Corporation
英文描述： Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路)
中文描述： 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路）
文件頁數(shù)： 5/33頁
文件大?。?/td> 176K
代理商： MT90810
Preliminary Information
MT90810
2-173
Device Overview
Mitel’s MT90810 is a MVIP compliant device. It
provides a complete, cost effective, MVIP compliant
interface between the MVIP Bus and a wide variety
of processors, telephony interfaces and other
circuits. The FMIC supports 384 full duplex, time
division
multiplexed
(TDM),
channels are divided into 256 full duplex MVIP
channels and 128 full duplex local channels. The
sample rate for each channel is 8kHz and the width
of each channel is 8 bits for a total data rate of
64kbits/s per channel.
channels.
These
The FMIC’s internal clock circuitry includes both an
analog and a digital PLL and supports all MVIP clock
modes. The device can be configured as a timing
master whereby an external 16.384MHz crystal or
4.096, 8.192 or 16.384MHz external clock source is
used to generate MVIP clock signals. The device can
also operate as a slave to the MVIP bus,
synchronizing its master clock to the MVIP 4MHz bus
clock.
The device’s local serial interface supports PCM
rates of 2.048, 4.096 and 8.192Mb/s, per channel
message mode, an additional control stream, as well
as parallel DMA through the microprocessor port.
Furthermore, the FMIC’s programmable group of
output framing signals and local output clocks may
be used to provide the appropriate frame and clock
pulses to drive other local serial buses such as GCI.
A microprocessor interface permits reading and
writing of the data memory, connection memory and
all internal control registers. The Connection and
Data memory can be read and updated while the
MVIP bus is active, that is, connections can be made
without interrupting bus activities.
Functional Description
Switching
The FMIC provides for switching of data from any
input channel to any output channel. This is
accomplished by buffering a single sample of each
channel in an on-chip 384 byte static RAM. Samples
are written into this data RAM in a fixed order and
read out in an order determined by the programming
of the connection memory. An input shift register and
holding latch for each input stream make up the
serial to parallel conversion blocks on the input of the
FMIC and an output holding register an shift register
make up the parallel to serial conversion blocks on
the output of the FMIC.
Data Memory
Data memory is a 384 byte static RAM block which
provides one sample of buffering for each of the 384
channels. An input shift register and holding latch for
each input stream make up the serial to parallel
conversion blocks on the input. Each input channel is
mapped to a unique location in the RAM, as shown
Table 18 - “Data Memory Mapping”.
Data memory can be read and written by the
microprocessor (See “Software Control” for further
details). Note that writing to data memory may be
futile since the contents will be overwritten by
incoming data on the serial input streams.
Connection Memory
Connection memory is comprised of a static RAM
block 384 locations by 12 bits. Each location in
connection memory corresponds to one of the 384
output channels. The mapping of memory location to
output channel is the same as the mapping of input
channel to data memory location and is shown in
Table 19 - “Connection Memory Mapping”.
The lower 8 bits of connection memory form
connection memory low byte as shown in Figure 10 -
“Connection Memory Low Byte”. The bits are defined
in Table 20, “Connection Memory Low Bits”.
The upper 4 bits of connection memory form
connection memory high (refer to Figure 11 -
“Connection memory high byte” ). Connection
memory low byte, together with the least significant
bit of connection memory high form an address to
point to in data memory. The location pointed to in
data memory provides the data for a given output
channel. The remaining three bits in connection
memory high are control bits. These bits perform
slightly different functions for MVIP and local
channels. The control bits in connection memory
high for MVIP streams enable/disable output drivers,
specify message or connection mode for individual
output channels, and determine the direction of the
DSi/DSo channel pair (see Table 21 - “Connection
Memory High Bits for MVIP channels” for further
details). The control bits in connection memory high
for local streams enable/disable DMA transfer,
specify message or connection mode for individual
output channels, and control CSTo timing (see Table
22 - “Connection Memory High Bits for Local
channels” for further details).
Connection memory can be read and written by the
microprocessor (see “Software Control” for further
details). When writing to connection memory, it is
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