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參數(shù)資料
| 型號： | NT5SV8M16FT-75BI |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 MM, PLASTIC, TSSOP2-54 |
| 文件頁數(shù)： | 18/65頁 |
| 文件大小： | 739K |
| 代理商： | NT5SV8M16FT-75BI |
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NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
25
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic
Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before
the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the
refresh cycle. No control of the external address pins is required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto
Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or
equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by hav-
ing CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the
Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is
internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self
Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is
cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device
exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus
the Self Refresh exit time (tSREX).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT5TU64M16DG-3C | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| NTA2425E | |
| NTA2425F | |
| NTA2410-10 | |
| NTD2410F | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5SV8M16HS-6K | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5SV8M8DT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-6K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
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