參數(shù)資料
型號(hào)： NT5SV8M16FT-75BI
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 MM, PLASTIC, TSSOP2-54
文件頁數(shù)： 24/65頁
文件大小： 739K
代理商： NT5SV8M16FT-75BI
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
30
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Enable (CKE) Truth Table
Current State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BA0,
BA1
A11 - A0
Self Refresh
H
X
INVALID
1
L
H
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
X
Exit Self Refresh with No Operation
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
X
ILLEGAL
2
L
X
Maintain Self Refresh
Power Down
H
X
INVALID
1
L
H
X
Power Down mode exit, all banks idle
2
L
H
L
X
ILLEGAL
2
L
X
Maintain Power Down Mode
All Banks Idle
H
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
H
X
3
H
L
H
X
3
H
L
H
X
CBR Refresh
H
L
OP Code
Mode Register Set
4
H
L
H
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
H
X
3
H
L
H
X
3
H
L
H
X
Entry Self Refresh
4
H
L
OP Code
Mode Register Set
L
X
Power Down
4
Any State
other than
listed above
H
X
Refer to operations in the Current State
Truth Table
H
L
X
Begin Clock Suspend next cycle
5
L
H
X
Exit Clock Suspend next cycle
L
X
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE
(tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising
clock after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-
tion.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
相關(guān)PDF資料
PDF描述
NT5TU64M16DG-3C 64M X 16 DDR DRAM, 0.45 ns, PBGA84
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NTA2425F
NTA2410-10
NTD2410F
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