參數(shù)資料
型號(hào)： NT5SV8M16FT-75BI
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 MM, PLASTIC, TSSOP2-54
文件頁(yè)數(shù)： 65/65頁(yè)
文件大?。?/td> 739K
代理商： NT5SV8M16FT-75BI
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
9
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank
Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select
address BA0 - BA1 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in
the selected bank.
The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the
Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS
delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be
applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is deter-
mined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands
(Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active
is specified as tRAS(max).
Bank Select
The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write oper-
ation.
Bank Activate Command Cycle
Bank Selection Bits
BA0
BA1
Bank
0
Bank 0
1
0
Bank 1
0
1
Bank 2
1
Bank 3
ADDRESS
CK
T0
T2
T1
T3
Tn
Tn+1
Tn+2
Tn+3
COMMAND
NOP
Bank A
Row Addr.
Bank A
Activate
Write A
with Auto
Bank A
Col. Addr.
. . . . . . . . . .
Bank B
Activate
Bank A
Row Addr.
Bank A
Activate
RAS-CAS delay (
tRCD)
: “H” or “L”
RAS Cycle time (
tRC)
Precharge
RAS - RAS delay time (
tRRD)
Bank B
Row Addr.
(CAS Latency = 3, tRCD = 3)
相關(guān)PDF資料
PDF描述
NT5TU64M16DG-3C 64M X 16 DDR DRAM, 0.45 ns, PBGA84
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
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