參數(shù)資料
型號(hào)： ORSO82G5-1FN680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 76/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
29
SONET TOH Byte Denitions
The Transport OverHead bytes of the SONET frame can be used for in-band conguration, service, and manage-
ment since it is carried along the same channel as data. In the ORSO42G5 and ORSO82G5 in-band signaling can
be efciently utilized, since the total cost of overhead is only 3.3%. The overhead bytes in an STS-1 header are
shown in Table 15 (The path overhead bytes are in the SPE.)
Figure 15. SONET Overhead Bytes
When used in true SONET applications, all or most TOH bytes will be generated in the FPGA logic or by an exter-
nal device. Two modes are provided for this application – transparent and AUTO_SOH. In transparent mode all
bytes from the FPGA logic are passed through unchanged.
In AUTO_SOH mode the embedded core inserts the A1/A2 framing bytes, performs the B1 calculation and inserts
the B1 byte. A1/A2 and B1 insertion can be independently enabled. This avoids the need to do SONET scrambling
in the FPGA logic. All other bytes are passed through unchanged from the FPGA logic as in transparent mode.
When used for applications that transfer non-SONET data, an AUTO_TOH mode is provided. In this mode, all of
the overhead bytes are set by the embedded core. Most of the bytes are set to zero. At the receive side, all of the
TOH bytes except those set to a non-zero value can be ignored in the AUTO_TOH mode.
The TOH bytes have the following functions in true SONET applications.
Section Overhead Bytes:
– A1, A2 – These bytes are used for framing and to mark the beginning of a SONET frame. A1 has the value
0x F6 and A2 has the value 0x28.
– J0 -Section Trace Message – This byte carries the section trace message. The message is interpreted to
verify connectivity to a particular node in the network.
– B1 - Section Bit Interleaved Parity (BIP-8) byte – This byte carries the parity information which is used to
check for transmission errors in a section. The computed parity value is transmitted in the next frame in the
B1 position. It is dened only for the rst STS-1 of a STS-N signal. The other bytes have a default value of
0x00.
J1
B3
C2
H4
G1
F2
Z4
Z5
Z6
A1
A2
J0
B1
E1
F1
D1
D2
D3
H1
H2
H3
B2
K1
K2
D4
D5
D6
D7
D8
D9
D10
D11
D12
S1/Z1
Z3
E2
J1
B3
C2
H4
G1
F2
Z4
Z5
Z6
0
1
4
3
2
5
6
7
8
Transport
Overhead
Path
Overhead
012
Line
Overhead
Section
Overhead
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參數(shù)描述
ORSO82G5-1FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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