參數(shù)資料
型號： ORSO82G5-1FN680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 94/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
45
Figure 31 shows the quad alignment mode in the ORSO42G5.
Figure 31. Receive SONET Mode, Quad Alignment Mode – ORSO42G5
SONET Mode Receive Timing – ORSO82G5
This section contains timing diagrams for major interfaces of this block to the FPGA logic when SONET frames are
to be transferred.
When operating in SONET mode, the entire SONET frame is sent to the FPGA. In multi-channel alignment
mode(s), data from all channels within an alignment group are aligned to the A1A2 framing bytes.
Each SONET frame is 125μs. The frame starts with 36 clock cycles (77.76 MHz) of TOH followed by 1044 clock
cycles of SPE, followed by 36 clock cycles of TOH, 1044 cycles of SPE.
The DOUTxx_SPE signal indicates TOH or SPE in the data (low for TOH, high for SPE)
Twin pairs are AA, AB (group A1), AC, AD (group A2), BA, BB (group B1) and BC, BD (group B2)
Figure 32 shows the SONET twin alignment mode timing for the ORSO82G5. The frame pulse and SPE indicators
are show for each of the two channels (AA, AB) in twin alignment.
Figure 32. Receive Clocking Diagram for SONET Mode Twin Alignment in Block A – ORSO82G5
...
1 cycle
36 cycles TOH
1044 cycles SPE
36 cycles TOH
Start of Frame
125 μs
Clocks
RSYSCLKA2 and RSYSYSCLKB2 are sourced by RCK78A
36 cycles TOH
Start of Frame
DOUTAC_FP
DOUTAD_FP
RSYSCLK[A2,B2]
DOUTBC_FP
DOUTBD_FP
RSYSCLKA1
DOUTAA[31:0]
DOUTAA_FP
TT
T
S
SS
T
SSSS
S
...
1 cycle
36 cycles TOH
1
044 cycles SPE
36 cycles TOH
Start of Frame
125 μs
Data
T Represents TOH
S Represents SPE
DOUTxx-SPE is high for SPE, low for TOH
Clocks
RSYSCLKA1 is the read clock used for group A1
RSYSCLKA2 is the read clock used for group A2
RSYSCLKB1 is the read clock used for group B1
RSYSBLKB2 is the read clock used for group B2
36 cycles TOH
TT
T
S
SS
T
SSSS
S
Start of Frame
DOUTAA_SPE
DOUTAB[31:0]
DOUTAB_SPE
DOUTAB_FP
相關PDF資料
PDF描述
PIC32MX775F256L-80I/PT IC MCU 32BIT 256K FLASH 100TQFP
VI-J4F-IW-F4 CONVERTER MOD DC/DC 72V 100W
PIC18LF8520-I/PT IC MCU FLASH 16KX16 EEPROM80TQFP
PIC18LF458-I/L IC MCU CAN FLASH 16K LP 44-PLCC
VI-J4F-IW-F2 CONVERTER MOD DC/DC 72V 100W
相關代理商/技術參數(shù)
參數(shù)描述
ORSO82G5-1FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*