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參數(shù)資料
| 型號(hào)： | ORSO82G5-1FN680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 77/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
3
High-speed SERDES programmable serial data rates of 0.6 Gbps to 2.7 Gbps.
Asynchronous operation per receive channel (separate PLL per channel).
Transmit pre-emphasis (programmable) for improved receive data eye opening.
Provides a 10 Gbps backplane interface to switch fabric using four work and, with the ORSO82G5, four protect
2.5 Gbit/s links. Also supports port cards at rates between 0.6 Gbps and 2.7 Gbps.
Allows wide range of applications for SONET network termination, as well as generic data moving for high-speed
backplane data transfer.
No knowledge of SONET/SDH needed in generic applications. Simply supply data (75 MHz-168.75 MHz clock)
and at least a single frame pulse.
High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
clocks.
Four- or eight-channel HSI functions provide 2.7 Gbps serial user data interface per channel for a total chip
bandwidth of >10Gbps or >20 Gbps (full duplex).
SERDES has low-power CML buffers and support for 1.5V/1.8V I/Os.
SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating
state.
Powerdown option of SERDES HSI receiver and/or transmitter on a per-channel basis.
Ability to mix half-rate and full-rate between the channels with the same reference clock.
Ability to congure each SERDES block independently with its own reference clock.
STS-48 framing in SONET mode.
Programmable enable of SONET scrambler/descrambler, A1/A2 insertion and B1 generation and checking.
Insertion and checking of link assignment values to facilitate interconnection and debugging of backplanes.
Optional AIS-L insertion during loss-of-frame.
Optional RDI-L insertion to indicate remote far-end defects for maintenance capabilities.
SPE signal marks payload bytes in SONET mode.
Frame alignment across multiple ORSO42G5 and ORSO82G5 devices for work/protect switching at STS-
768/STM-256 and above rates.
Supports transparent mode where Transport OverHead (TOH) bytes are user-generated in the FPGA.
Supports two modes of in-band management and conguration with TOH byte extraction/insertion by the
Embedded core. A1/A2 and B1 insertion can be independently enabled.
– AUTO_SOH where the embedded core inserts the A1/A2 framing bytes, performs the B1 calculation and
inserts the B1 byte. All other bytes are passed through unchanged from the FPGA logic as in transparent
mode.
– AUTO_TOH where all of the overhead bytes are set by the embedded core. Most of the bytes are set to zero.
At the receive side, all of the TOH bytes except those set to a non-zero value can be ignored.
Optional A1/A2 corruption, B1 byte corruption, and K2 byte corruption for system debug purposes.
Built-in boundary scan (IEEE 1149.1 and 1149.2 JTAG), including the SERDES interface.
FIFOs align incoming data across all eight channels (ORSO82G5 only), groups of four channels, or groups of
two channels. Optional ability to bypass alignment FIFOs for asynchronous operation between channels is also
provided. (Each channel includes its own recovered clock and frame pulse).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-2F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-2F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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