SECTION 5
PCI 9080
PIN DESCRIPTION
PLX Technology, Inc., 1997
Page 92
Version 1.02
Table 5-5. Local Bus Mode and Processor Independent Interface Pin Description
Symbol
Signal Name
Total
Pins
Pin
Type
Pin
Number
Function
ADMODE
Address Decode
Mode
1
I
20
Determines how S[2:0] are used to access the PCI 9080 internal
registers.
BIGEND#
Big Endian Select
1
I
48
Can be asserted during the local bus address phase of a Direct
Master transfer or a configuration register access to specify use of Big
Endian byte ordering. Big Endian byte order for Direct Master
transfers or configuration register accesses is also programmable
through configuration registers.
BPCLKo
Buffered PCI Clock
Output
1
O
TP
8 mA
168
Provides a buffered PCI clock output.
BREQ
Bus Request
1
I
169
Asserted to indicate a local bus master requires the bus. If enabled
through the PCI 9080 configuration registers, PCI 9080 releases the
bus during a DMA transfer if this signal is asserted.
BREQo
Bus Request Out
1
O
TP
8 mA
21
Asserted to indicate the PCI 9080 requires the bus to perform a direct
PCI to local bus access while a Direct Master access is pending on
the local bus. It can be used with external logic to generate backoff to
a local bus master. Its operational parameters are set up through the
PCI 9080 configuration registers.
BTERMo#
Burst Terminate Out
1
O
DTS
8 mA
28
Asserted, along with READYo#, to request the break up of a burst
and the start of a new address cycle (Abort only).
DACK[1:0]#
DMA Acknowledge
Outputs
2
O
TP
8 mA
25, 30
When a channel is programmed through the configuration registers to
operate in demand mode, its DACK output indicates a DMA transfer is
being executed. DACK0# corresponds to PCI 9080 DMA Ch 0 and
DACK1# to DMA Ch 1.
DMPAF#
Direct Master
Programmable Almost
Full
1
O
TP
8 mA
8
Direct Master write FIFO almost full status output. Programmable
through a configuration register.
DP[3:0]
Data Parity
4
I/O
TS
8 mA
12-15
Parity is even for each of up to 4 byte lanes on the local bus. Parity is
checked for writes to the PCI 9080 or reads by the PCI 9080. Parity is
generated for reads from the PCI 9080 or writes by the PCI 9080.
DREQ[1:0]#
DMA Request Inputs
2
I
24, 29
When a channel is programmed through the configuration registers to
operate in demand mode, its DREQ input serves as a DMA request.
DREQ0# corresponds to PCI 9080 DMA Ch 0 and DREQ1# to DMA
Ch 1.
LDSHOLD
Direct Slave HOLD
Request
1
O
TP
8 mA
165
Asserted concurrent with LHOLD to indicate the PCI 9080 is
requesting use of the Local Bus in order to perform a Direct Slave
transfer.
LINTi#
Local Interrupt In
1
I
151
When asserted low, causes a PCI interrupt.
LINTo#
Local Interrupt Out
1
O
TP
8 mA
152
Synchronous level output that remains asserted as long as an
interrupt condition exists. If an edge level interrupt is required,
disabling and then enabling local interrupts though the Interrupt
Control/Status Register (refer to Table 4-58) creates an edge if an
interrupt condition still exists or a new interrupt condition occurs.
LLOCKo#
Bus Lock
1
O
TP
8 mA
7
Indicates an atomic operation for a Direct Slave PCI to local bus
access may require multiple transactions to complete.
LRESETi#
Local Reset Input
1
I
150
Resets the local bus portion of the PCI 9080, the local configuration
registers and the DMA configuration registers. Also causes local reset
output to be asserted.