參數(shù)資料
型號(hào)： PCI9060
廠商： Electronic Theatre Controls, Inc.
英文描述： 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
中文描述： 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng)
文件頁(yè)數(shù)： 42/192頁(yè)
文件大?。?/td> 1551K
代理商： PCI9060
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 33
Version 1.02
DREQ[1:0]# is de-asserted, the second Lword is not
transferred.
DREQ[1:0]# controls only the number of Lword transfers.
For an 8-bit bus, PCI 9080 gives up the bus after the last
byte for the Lword is transferred. For a 16-bit bus, PCI
9080 gives up the bus after the last word for the Lword is
transferred.
3.7.5 DMA Priority
DMA Channel 0 priority, DMA Channel 1 priority, or
rotating priority can be specified in the DMA Arbitration
Register.
3.7.6 DMA Arbitration
PCI 9080 DMA controller releases control of the local
bus (de-asserts LHOLD) when one of the following
occurs:
FIFOs are full in a local to PCI transfer
FIFOs are empty in a PCI to local transfer
Local Bus Latency Timer expires (if enabled)
BREQ input is asserted (BREQ can be enabled or
disabled, or gated with a latency timer before the
PCI 9080 gives up the local bus)
Direct Slave access is pending
EOT input is received (if enabled)
DMA controller releases control of the PCI bus when one
of the following occurs:
FIFOs are full or empty
PCI Latency Timer expires and loses the PCI grant
signal
Target Disconnect response received
DMA controller de-asserts its PCI bus request (REQ#)
for a minimum of two PCI clocks.
3.7.6.1 End of Transfer (EOT0# or EOT1#)
Input
DMA Mode Register bit 14 (BLAST mode for EOT),
determines the number of Lwords transferred after a
DMA controller EOT[1:0]# input is asserted.
If BLAST# output is not required for the last Lword of the
DMA transfer (bit 14 = 1), the DMA controller releases
the data bus and terminates DMA after it receives an
external READYi# or the internal wait state counter
decrements to a value of 0 for the current Lword. If the
DMA controller is currently bursting data, which is not
the last data phase for the burst, BLAST# output will not
be asserted.
If BLAST# output is required for the last Lword of the
DMA transfer (bit 14 = 0), the DMA controller transfers
one or two Lwords. If EOT[1:0]# is asserted, the DMA
controller completes the current Lword, and one
additional Lword (this allows BLAST# output to be
asserted during the final Lword). If DMA FIFO is
full/empty after the data phase in which EOT[1:0]# is
asserted, the second Lword is not transferred.
DMA controller terminates a transfer on an Lword
boundary after EOT[1:0]# is asserted. For an 8-bit bus,
PCI 9080 terminates after the last byte for the Lword is
transferred. For a 16-bit bus, PCI 9080 terminates after
the last word for the Lword is transferred.
3.7.6.2 DMA Abort
A DMA transfer can be aborted. The abort process is as
follows:
1.
DMA Channel must be enabled (Table 4-72[0]=1).
2.
DMA Channel must be started (Table 4-72[1]=1).
3.
Wait for the Channel Done bit to be set to zero
(Table 4-72[4]=0).
4.
Disable the DMA Channel (Table 4-72[0] =0).
5.
Abort DMA by programming the Channel Abort bit
(Table 4-72[2]=1).
6.
Wait until the Channel Done bit is set (Table 4-
72[4]=1).
Note:
One to two data transfers occur after the abort
bit is set. Aborting when no DMA cycles are in progress
causes the next DMA to abort.
3.7.6.3 Local Latency and Pause Timers
A Local Bus Latency Timer and Local Bus Pause Timer
are programmable with the DMA Arbitration Register. If
local latency timer expires, PCI 9080 completes the
current Lword transfer and releases LHOLD. After its
programmable Pause Timer expires, it reasserts
LHOLD. When it receives LHOLDA, it continues the
transfer. PCI bus transfer continues until the FIFO is
empty for a local to PCI transfer or until it is full for a PCI
to local transfer.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI90603A 制造商:PLX Technology 功能描述:
PCI9060-3A 制造商:PLX Technology 功能描述:
PCI9060-3AF 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9060ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PCI9060ESF 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
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