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參數(shù)資料
| 型號(hào)： | PCI9060 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁(yè)數(shù)： | 28/192頁(yè) |
| 文件大小： | 1551K |
| 代理商： | PCI9060 |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 19
Version 1.02
PCI Configuration Address Register for Direct
Master to PCI IO/CFG
PCI Base Address
3.6.1.1 Decode
The Range register specifies the local address bits to
use for decoding a Local to PCI access. The local
processor can perform only memory cycles. Therefore,
the Local Base Address for Direct Master to PCI Memory
Register is used to decode an access to PCI memory
space and the Local Base Address for Direct Master to
PCI IO/CFG Register is used to decode an access to
PCI I/O space or PCI bus configuration cycle access.
3.6.1.2 FIFOs
For Direct Master memory access to the PCI bus, PCI
9080 has a 32 Lword (128 byte) write FIFO and a 16
Lword (64 byte) read FIFO. FIFOs enable the local bus
to operate independently of the PCI bus and allows high-
performance bursting on local and PCI buses. In a Direct
Master Write, the local processor (Master) writes data to
PCI (Slave). In a Direct Master Read, the local processor
(Master) reads data from PCI (Slave). Figure 3-6 and
Figure 3-7 illustrate the FIFOs during a Direct Master
Write and Read.
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Figure 3-6. Direct Master Write
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Figure 3-7. Direct Master Read
3.6.1.3 Memory Access
The local processor can read or write to the PCI
memory. PCI 9080 converts the local read/write access.
The Local Address space starts from the Direct Master
Local Base Address up to the range. Remap (PCI Base
Address) defines the PCI starting address.
Writes
—PCI 9080 continues to accept writes and return
READYo# until write FIFO is full. It then holds off
READYo# until space becomes available in the write
FIFO. A programmable Direct Master FIFO “almost full”
status output is provided (DMPAF#).
Reads
—PCI 9080 holds off READYo# while gathering
an Lword from the PCI bus. Programmable prefetch
modes are available if prefetch is enabled: prefetch, 4, 8,
16, or continuous until Direct Master cycle ends. The
read cycle is terminated when the local BLAST# input is
asserted. Unused read data is flushed from the FIFO.
PCI 9080 does not prefetch read data for single cycle
Direct Master reads (local BLAST# input asserted during
first data phase). In this case, PCI 9080 reads a single
PCI Lword.
For Direct Master single cycle reads, PCI 9080 asserts
the same PCI bus byte enables as asserted on the local
bus.
For multiple cycle reads, PCI 9080 reads entire Lwords
(all PCI byte enables are asserted), regardless of local
byte enables.
If the prefetch limit bit DMPBAM (PCI:28h)(LOC:A8h)
(refer to Table 4-43[11]) is enabled, PCI 9080 does not
prefetch past a 4K boundary. Also, the local side must
not cross a 4K boundary during a burst read.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI9080 | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060ES | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI950PT | PC Card Support |
| PCI9656-AC66BI | Controller Miscellaneous - Datasheet Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI90603A | 制造商:PLX Technology 功能描述: |
| PCI9060-3A | 制造商:PLX Technology 功能描述: |
| PCI9060-3AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
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