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參數(shù)資料
| 型號： | PEB2445N |
| 廠商： | SIEMENS AG |
| 英文描述： | LTM4600 Evaluation Kit |
| 中文描述： | ？多點交換和會議股-衰減？ |
| 文件頁數(shù)： | 32/70頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | PEB2445N |
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PEB 2445
Functional Description
Semiconductor Group
32
02.96
Configuration Type
The MUSAC-A works either in the standard configuration for usual switching
applications or in the primary access configuration. In these both configurations the
conference and multipoint switching capability can be used.
Standard Configuration
A logical 1 in the
CFS
bit of the configuration register sets the PEB 2445 in standard
mode (default after power up). All modes from
table 7
can be used. It has to be ensured
that the data rate is not higher than the selected device clock (4096 or 8192 kHz).
In this application 512 channels per frame are written into the speech memory. Each one
of them can be connected to any output channel.
Any output channel can be attenuated independently of each other.
According to
table 8
and
table 12
and depending on the selected mode the least
significant bits of the connection memory address and data contain the logical pin
numbers, the most significant bits the time-slot number of the output and input channels.
The following example explains the programming sequence.
Time-slot 7 of the incoming 8192-kbit/s input line IN 14 shall be connected to time-slot 6
of the output line OUT 5 of an 2048-kbit/s system. The attenuation for this connection
should be 7 dB. According to
table 8
in 8192-kbit/s systems the input line IN 14 is the
logical input line 2. Output line number and logical output number are identical to one
another. According to
chapter 4.5
C3
…
C0 is set to 7
H
.
Therefore the following byte sequence on the address data bus has to be used to
program the CM properly (see
table 12
):
01101100
(Control Byte)
or
00011110
(Data Byte)
00110101
(Address Byte)
The frame, for all input channels, starts with the rising edge of the SP signal. The frame
for all output channels begins two
t
CP8
(with 8192-kHz device clock) or one
t
CP4
period
(4096-kHz device clock) before the falling SP edge. The period of time between the
rising and falling edge of the SP pulse should be
t
SPH
= (2 + N
×
4)
t
CP8
(0
≤
N
≤
255)
= (1 + N
×
2)
t
CP4
01011100
00011110
00110101
(Control Byte)
(Data Byte)
(Address Byte)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PEB2445-N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| PEB2445P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM， Other/Special/Miscellaneous |
| PEB2447 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447H | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447HV1.2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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