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參數(shù)資料
| 型號(hào)： | PEB2445N |
| 廠商： | SIEMENS AG |
| 英文描述： | LTM4600 Evaluation Kit |
| 中文描述： | ？多點(diǎn)交換和會(huì)議股-衰減？ |
| 文件頁數(shù)： | 54/70頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | PEB2445N |
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PEB 2445
Detailed Register Description
Semiconductor Group
54
02.96
4.6.2
Access: Read or write at address FF
H
Reset value: 00
H
Clock Shift Register (CSR)
RS2
…
RS0
Receive
clock
Shift
, bits 2 – 0. The received data stream is shifted in bit
period steps.
Receive
with
Rising Edge
. The data is sampled with the falling
(RRE = 0) or rising edge (RRE = 1) of the data equivalent clock.
Transmit
clock
Shift
, bits 2 – 0. The transmitted data stream is shifted.
Transmit
with
Falling Edge
; data is transmitted with the rising
(XFE = 0) or falling edge (XFE = 1) of the device clock.
Data stream manipulation according to these register entries only affects the system
interface and only in the primary access configuration. The frame structure can be
moved relative to the SP slope by up to 7 clock periods in half clock period steps. This
register can hold non-zero values only for a CFR:CFS value of logical 0.
Identical non-zero entries for RS2 – RS0 and XS2 – XS0 as well as identical RRE and
XFE generate an output time-slot structure which is 1 time-slot late relative to the input
time-slot structure.
Identical 000 entries for RS2 – RS0 and XS2 – XS0 as well as RRE and XFE being
logical 0 cause the input and output frames to coincide in time.
RRE
XS0
…
XS2
XFE
AD7
AD0
RS2
RS1
RS0
RRE
XS2
XS1
XS0
XFE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEB2445-N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| PEB2445P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM， Other/Special/Miscellaneous |
| PEB2447 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447H | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447HV1.2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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