參數(shù)資料
型號(hào)： PEF2015
廠商： SIEMENS A G
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Mini IOM-2 Controller MICO
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO28
文件頁(yè)數(shù)： 15/84頁(yè)
文件大?。?/td> 1568K
代理商： PEF2015
PEF 2015
Functional Description
Semiconductor Group
15
12.97
2.3
The MICO supports Siemens/Intel and Motorola type microprocessors. In the Siemens/
Intel type
μ
P interface either a multiplexed or a demultiplexed bus structure may be
chosen.
The interface type is selected by pulling up or down two address pins during the reset
state (refer to
Table 1, “Selection of Bus Interface,” on page 18
). Pulling-up the
appropriate pins selects the Motorola type
μ
P interface, fixing them to ground chooses
the Siemens/Intel type
μ
P interface mode. In case of a multiplexed Siemens/Intel bus
structure address pin A0 takes over the ALE functionality.
The microprocessor interface consists of the following lines:
Data Bus, 8-bit wide, AD7..AD0
Address bus, 4-bit wide, A3..A0
Chip select, CS
Two read/write control lines: RD and WR (Intel mode) or DS and R/W (Motorola mode)
Interrupt, INT
Reset, RES
Microprocessor Interface
Figure 5
Selectable Bus Interface Structures
2.4
Memory Structure and Switching
The memory block of the MICO performs the switching functionality.
It consists of four sub blocks:
– Upstream data memory
– Downstream data memory
– Upstream control memory
– Downstream control memory.
The PCM-interface reads periodically from the upstream (writes periodically to the
downstream) data memory (cyclical access), see
figure
6.
The CFI reads periodically the control memory and uses the extracted values as a
pointers to write to the upstream (read from the downstream) data memory (random
BUS_INTF.DRW
Address/Data Bus
Interface,
with Siemens/Intel Type
MICO
MICO
with Motorola
Type Interface
MICO
with Siemens/Intel Type
Address/Data Bus
DS
CS
D0-7
0-3
A
R
/
W
A
0-3
0-7
D
CS
RD
0-7
AD
CS
RD
ALE
WR
WR
Demultiplexed
Multiplexed
Interface,
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