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參數(shù)資料
| 型號： | PEF2015 |
| 廠商： | SIEMENS A G |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Mini IOM-2 Controller MICO |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 文件頁數(shù)： | 65/84頁 |
| 文件大?。?/td> | 1568K |
| 代理商： | PEF2015 |
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PEF 2015
Registers Summary
Semiconductor Group
65
12.97
4.2.6.5
Access in demultiplexed
μ
P-interface mode:
Interrupt Status Register (ISTA)
read
address: E
H
OMDR:RBS = 0
Access in multiplexed
μ
P-interface mode:
Reset value: 00
H
read
address: 1C
H
The ISTA-register should be read after an interrupt in order to determine the interrupt
source.
TIN
Timer
CMDR:ST,TIG = 1 has occurred. The TIN-bit is reset by reading ISTA. It
should be noted that the interrupt generation is periodic, i.e. unless stopped
by writing to TIMR, the ISTA:TIN will be generated each time the timer
expires.
Signaling FIFO-Interrupt; this interrupt is generated if there is at least one
valid entry in the CIFIFO indicating a change in a C/I- or SIG-channel.
Reading ISTA does not clear the SFI-bit. Instead SFI is cleared if the CIFIFO
is empty which can be accomplished by reading all valid entries of the
CIFIFO or by resetting the CIFIFO by setting CMDR:CFR to 1.
MFFIFO-Interrupt;
the
last
MF-channel
CMDR:MFT1,MFT0) has been executed and the MICO is ready to accept the
next
command.
Additional
information
STAR:MFTO…MFFE. MFFI is reset by reading ISTA.
Monitor channel Active interrupt; the MICO has found an active monitor
channel. A new search can be started by reissuing the CMDR:MFSO-
command. MAC is reset by reading ISTA.
PCM-Framing Interrupt; the STAR:PSS-bit has changed its polarity. To
determine whether the PCM-interface is synchronized or not, STAR must be
read. The PFI-bit is reset by reading ISTA.
Synchronous Transfer Interrupt; The SIN-interrupt is enabled if at least one
synchronous transfer channel (A and/or B) is enabled via the STCR:TAE,
TBE-bits. The SIN-interrupt is generated when the access window for the
μ
P
opens. After the occurrence of the SIN-interrupt the
μ
P can read and/or write
the synchronous transfer data registers (STDA, STDB). The SIN-bit is reset
by reading ISTA.
interrupt;
a
timer
interrupt
previously
requested
with
SFI
MFFI
command
(issued
by
can
be
read
from
MAC
PFI
SIN
bit 7
bit 0
TIN
SFI
MFFI
MAC
PFI
0
SIN
SOV
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