參數(shù)資料
型號(hào)： PEF2015
廠商： SIEMENS A G
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Mini IOM-2 Controller MICO
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO28
文件頁(yè)數(shù)： 19/84頁(yè)
文件大?。?/td> 1568K
代理商： PEF2015
PEF 2015
Operational Description
Semiconductor Group
19
12.97
RBS = ’1’ selects a set of registers used for device initialization (e.g. CFI and PCM
interface initialization).
RBS = ’0’ switches to a group of registers necessary during operation (e.g. connection
programming).
The OMDR register containing the RBS bit can be accessed with either value of RBS.
Interrupts
An interrupt of the MICO is indicated by activating the INT-line. The detailed cause of the
request can be determined by reading the ISTA register.
The INT-output is level active. It stays active until all interrupt sources have been
serviced. If a new status bit is set while an interrupt is being serviced, the INT stays
active. However, for the duration of a write access to the MASK-register the INT-line is
deactivated. When using an edge-triggered interrupt controller, it is thus recommended
to rewrite the MASK-register at the end of any interrupt service routine.
Every interrupt source can be selectively masked by setting the respective bit of the
MASK-register. Such masked interrupts will not be indicated in the ISTA-register, nor will
they activate the INT-line.
3.2
Clocking
To operate properly, the MICO always requires a PDC-clock.
To synchronize the PCM-side, the MICO should normally also be provided with a PFS-
strobe. In most applications, the DCL and FSC will be output signals of the MICO,
derived from the PDC via prescalers.
If the required CFI-data rate cannot be derived from the PDC, DCL and FSC can also be
programmed as input signals. This is achieved by setting the MICO CMD1:CSS-bit.
Frequency and phase of DCL and FSC may then be chosen almost independently of the
frequency and phase of PDC and PFS. However, the CFI-clock source
must
still be
synchronous to the PCM-interface clock source; i.e. the clock source for the CFI-
interface and the clock source for the PCM-interface must be derived from the same
master clock.
3.3
Reset
A reset pulse of at least 4 PDC clock cycles has to be applied at the RES pin. The reset
pulse sets all registers to their reset values described in
section 4
.
The MICO is now in CM-reset mode (refer to
4.2.6.7
). As the hardware reset does not
affect the MICO memories CM and DM, a ’software reset’ of the CM has to be performed.
Subsequently the MICO can be programmed to CM-initialization, normal operation or
test mode.
During reset the address pins A0 and A1 are evaluated to determine the bus interface
type.
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