參數(shù)資料
型號: Pentium II 333
廠商: Intel Corp.
英文描述: Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器)
中文描述: 而對整個處理器模高速緩存低功率模塊(帶片上緩存低能量模塊的處理器)
文件頁數(shù): 13/50頁
文件大?。?/td> 1123K
代理商: PENTIUM II 333
Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
13
PHOLD#
I
PCI
V_3
PCI Hold:
This signal comes from the expansion bridge; it is the
bridge request for PCI.
The 82443BX Host Bridge/Controller will
drain the DRAM write buffers, drain the processor-to-PCI posting
buffers, and acquire the host bus before granting the request via
PHLDA#. This ensures that GAT timing is met for ISA masters.
The
PHOLD# protocol has been modified to include support for passive
release.
PHLDA#
O
PCI
V_3
PCI Hold Acknowledge:
This signal is driven by the 82443BX
Host Bridge/Controller to grant PCI to the expansion bridge.
The
PHLDA# protocol has been modified to include support for passive
release.
PAR
I/O
PCI
V_3
Parity:
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
SERR#
I/O
PCI
V_3
System Error:
The 82443BX asserts this signal to indicate an error
condition. Refer to the Intel
440BX AGPset: Host Bridge/Controller
datasheet for further information.
CLKRUN#
I/O D
PCI
V_3
Clock Run:
An open-drain output and input.
The 82443BX Host
Bridge/Controller requests the central resource (PIIX4E) to start or
maintain the PCI clock by asserting CLKRUN#.
The 82443BX Host
Bridge/Controller three-states CLKRUN# upon deassertion of
Reset (since CLK is running upon deassertion of Reset).
PCI_RST#
I
CMOS
V_3
Reset:
When asserted, this signal asynchronously resets the
82443BX Host Bridge.
The PCI signals also three-state, compliant
with PCI Rev 2.1 Specifications
Table 4. PCI Signal Descriptions (Sheet 2 of 2)
Name
Type
Voltage
Description
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