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參數(shù)資料
| 型號(hào)： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
23
consumption while the system is idle, the internal 82443BX Host Bridge/Controller clock is
turned off (gated off) when there is no processor and PCI activity. This is accomplished by
setting the G_CLK enable bit in the power management register in the 82443BX through the
system BIOS.
4.3.1
Memory Organization
The memory interface of the 82443BX Host Bridge/Controller is available at connector. This
allows for the following:
One set of memory control signals, sufficient to support up to three SO-DIMM sockets and six
banks of SDRAM at 66 MHz.
One CKE signal for each bank.
Memory features not supported by the 82443BX Host Bridge/Controller standard mode are:
Support for eight banks of memory.
Second set of memory address lines (MAA[13:0]).
DRAM technologies supported by the 82443BX Host Bridge/Controller include EDO and
SDRAM. These memory types may not be mixed in the system, so that all DRAM in all rows
(RAS[5:0]#) must be of the same technology. The 82443BX Host Bridge/Controller targets 60
nanoseconds EDO DRAMs and 66-MHz SDRAMs.
The module’s clocking architecture supports the use of SDRAM. Tight timing requirements of the
66-MHz SDRAM clocks allow all host and SDRAM clocks to be generated from the same
clocking architecture. For complete details about using SDRAM memory, and for trace length
guidelines, see the
Pentium
II Processor – Low Power Module at 266 MHz 66 MHz SDRAM
DIMM Routing Guidelines
(order number 273230). Refer to the
Intel
440BX AGPset: 82443BX
Host Bridge/Controller
datasheet for details on memory device support, organization, size, and
addressing.
4.3.2
Reset Strap Options
Several strap options on the memory address bus define the behavior of the module after reset.
Other straps can override the default settings. Table 15 shows the straps and their implementation.
Table 15. Configuration Straps for the 82443BX Host Bridge/Controller
Signal
Function
Module Default Setting
Optional Override on
System Electronics
MAB[12]#
Host Frequency Select
No strap
66 MHz default.
None
MAB[11]#
In Order Queue Depth
No strap
maximum queue depth is
set, i.e., 8.
None
MAB[10]
Quick Start Select
Strapped high on the module for
Quick Start mode.
None
MAB[9]#
AGP disable
No strap
AGP is enabled.
Pull up this signal to disable
the AGP interface.
MAB[7]#
MM Config
No strap-standard mode.
None
MAB[6]#
Host Bus Buffer Mode
Select
Strapped high on the module for
PSB buffers.
None
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