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參數(shù)資料
| 型號(hào)： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 26/50頁 |
| 文件大小： | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
26
Datasheet
4.4.2
Normal State
This is the normal operating mode where the processor’s core clock is running and the processor is
actively executing instructions.
4.4.3
Auto Halt State
This is a low power mode entered by the processor through the execution of the HLT instruction.
The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is
made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#, INIT#,
RESET#, FLUSH#, or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to
the Stop Grant state or the Quick Start state, where a Stop Grant Acknowledge bus cycle will be
issued. Deasserting STPCLK# will cause the processor to return to the Auto Halt state without
issuing a new Halt bus cycle.
The SMI# (System Management Interrupt) is recognized in the Auto Halt state. The return from the
SMI handler can be to either the Normal state or the Auto Halt state. See the
Intel
Architecture
Software Developer’s Manual, Volume III: System Programmer’s Guide
for more information. No
Halt bus cycle is issued when returning to the Auto Halt state from System Management Mode
(SMM).
The FLUSH# signal is serviced in the Auto Halt state. After flushing the on-chip, the processor
will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in the A20M# and
PREQ# signals are recognized while in the Auto Halt state.
4.4.4
Stop Grant State
Important:
This state is not available on the module.
The processor enters this mode with the assertion of the STPCLK# signal when it is configured for
Stop Grant state (via the A15# strapping option). The processor is still able to respond to snoop
requests and latch interrupts. Latched interrupts will be serviced when the processor returns to the
Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the
Normal state can be made by the deassertion of the STPCLK# signal, or the occurrence of a stop
break event (a BINIT#, FLUSH#, or RESET# assertion).
The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization
unless STPCLK# has been deasserted. RESET# assertion will cause the processor to immediately
initialize itself. However, the processor will stay in the Stop Grant state after initialization until
STPCLK# is deasserted. If the FLUSH# signal is asserted, the processor will flush the on-chip
caches and return to the Stop Grant state. A transition to the Sleep state can be made by the
assertion of the SLP# signal.
While in the Stop Grant state, assertions of SMI#, INIT#, INTR, and NMI (or LINT[1:0]) will be
latched by the processor. These latched events will not be serviced until the processor returns to the
Normal state. Only one of each event will be recognized upon return to the Normal state.
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