參數(shù)資料
型號(hào)： Pentium II 333
廠商： Intel Corp.
英文描述： Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器)
中文描述： 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器）
文件頁(yè)數(shù)： 33/50頁(yè)
文件大?。?/td> 1123K
代理商： PENTIUM II 333
Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
33
4.7.2
Control of the Voltage Regulator
The VR_ON pin turns the DC voltage regulator on or off. The VR_ON pin should be controlled as
a function of the SUSB#, which controls the system’s power planes. VR_ON should switch high
only when the following conditions are met: V_5(s)
≥
4.5 V and V_DC
≥
4.75 V.
Caution:
Turning on VR_ON prior to meeting these conditions will severely damage the module
.
The VR_PWRGD signal indicates that the voltage regulator power is operating at a stable voltage
level. Use VR_PWRGD on the system electronics to control power inputs and to gate PWROK to
the PIIX4E.
Table 22 lists the voltage signal definitions and sequences, and Figure 5 shows the signal
sequencing and the voltage planes sequencing required for normal operation of the module.
4.7.2.1
Voltage Signal Definition and Sequencing
Table 22. Voltage Signal Definitions and Sequences
Signal
Source
Definitions and Sequences
V_DC
System Electronics
V_DC is required to be between 5 V and 21 V DC and is driven
by the system electronics’ power supply. V_DC powers the
module’s DC-to-DC converter for the processor core and I/O
voltages. The module cannot be hot inserted or removed while
V_DC is powered on.
V_3
System Electronics
V_3 is supplied by the system electronics for the 82443BX.
V_5
System Electronics
V_5 is supplied by the system electronics for the 82443BX’s 5 V
reference voltage and the module’s voltage regulator.
VR_ON
System Electronics
VR_ON is a 3.3 V (5 V tolerant) signal that enables the module’s
voltage regulator circuit. When driven active high the voltage
regulator circuit is activated. The signal driving VR_ON should
be a digital signal with a rise/fall time of less than or equal to
1 μs. (V
IL
(max)=0.4V, V
IH
(min)=3.0V).
V_CORE (also a
host bus GTL+
termination
voltage VTT)
Module
A result of VR_ON being asserted, V_CORE is an output of the
DC-DC regulator on the module and is driven to the core voltage
of the processor. It is also used as the host bus GTL+
termination voltage, known as VTT.
VR_PWRGD
Module
Upon sampling the voltage level of V_CORE (minus tolerances
for ripple), VR_PWRGD is driven active high. If VR_PWRGD is
not sampled active within 1 second of the assertion of VR_ON,
then the system electronics should deassert VR_ON. After
V_CORE is stabilized, VR_PWRGD will assert to logic high
(3.3V). This signal
must not be pulled up
by the system
electronics. VR_PWRGD should be “ANDed” with V_3s to
generate the PIIX4E input signal, PWROK. The system
electronics should monitor VR_PWRGD to verify it is asserted
high prior to the active high assertion of PIIX4E PWROK.
V_CPUPU
Module
V_CPUPU is 2.5 V. The system electronics use this voltage to
power the PIIX4E-to-processor interface circuitry.
V_CLK
Module
V_CLK is 2.5 V. The system electronics use this voltage to
power the HCLK[0:1] drivers for the processor clock.
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