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參數(shù)資料
| 型號(hào)： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 30/50頁 |
| 文件大小： | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
30
Datasheet
4.6.2
AC Requirements
Table 19 shows the BCLK AC requirements.
4.6.2.1
PSB Clock Signal Quality Specifications and
Measurement Guidelines
Table 20 describes the signal quality specifications at the processor core for the processor system
bus (PSB) clock (BCLK) signal.
Figure 4 describes the signal quality waveform for the PSB clock at the processor core pins.
Table 19. AC Specifications at the Processor Core Pins
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
1,2
PSB Frequency
3
66.67
MHz
All processor core
frequencies
T1: BCLK Period
3,4
15.0
ns
T2: BCLK Period Stability
5,6,7
±250
ps
T3: BCLK High Time
5.3
ns
At >1.8 V
T4: BCLK Low Time
5.3
ns
At <0.7V
T5: BCLK Rise Time
7
0.175
0.875
ns
(0.9 V-1.6 V)
T6: BCLK Fall Time
7
0.175
0.875
ns
(1.6 V–0.9 V)
NOTES:
1. All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All GTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core
pins.
2. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.
3. The internal core clock frequency is derived from the PSB clock. The PSB clock to core clock ratio is
determined during initialization as described and is predetermined by the module.
4. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the
CK97 Clock
Synthesizer/Driver Specification
for further information.
5. Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a
component of BCLK skew between devices.
6. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The -20 dB attenuation point, as measured into a 10 pF to a 20 pF load,
should be less than 500 kHz. This specification may be ensured by design characterization and/or
measured with a spectrum analyzer. See the
CK97 Clock Synthesizer/Driver Specification
for further details.
7. Not 100% tested. Specified by design characterization as a clock driver requirement.
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