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參數(shù)資料
| 型號： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對整個處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 24/50頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
24
Datasheet
4.3.3
PCI Interface
The PCI interface of the 82443BX Host Bridge/Controller is available at the connector. The
82443BX Host Bridge/Controller supports the PCI Clockrun protocol for PCI bus power
management. In this protocol, PCI devices assert the CLKRUN# open-drain signal when they
require the use of the PCI interface.
The 82443BX Host Bridge/Controller is responsible for arbitrating the PCI bus. With the module
connector, the 82443BX Host Bridge/Controller can support up to five PCI bus masters. There are
five PCI Request/Grant pairs, REQ[4:0]# and GNT[4:0]#, available on the connector to the
manufacturer’s system electronics.
Note:
The PCI interface on the module connector is 3.3 V only. 5 V PCI devices are not supported such
as all devices that drive outputs to a 5
Vt
nominal V
oh
level.
The 82443BX Host Bridge/Controller is compliant with the PCI Rev. 2.1 specification, which
improves the worst case PCI bus access latency from earlier PCI specifications. The 82443BX
Host Bridge/Controller supports only Mechanism #1 for accessing PCI configuration space, as
detailed in the PCI specification. This implies that signals AD[31:11] are available for PCI IDSEL
signals. However, since the 82443BX Host Bridge/Controller is always device #0, AD11 will never
be asserted during PCI configuration cycles as an IDSEL. The 82443BX reserves AD12 for the
AGPbus. Thus, AD13 is the first available address line usable as an IDSEL. Intel recommends that
AD18 be used by the PIIX4E.
4.3.4
AGP Interface
The 82443BX Host Bridge/Controller is compliant with the AGP Interface Specification Rev 1.0,
which supports an asynchronous AGP interface coupling to the 82443BX core frequency. The
AGP interface can achieve real data throughput in excess of 500 Mbytes/s using an AGP 2X
graphics device. Actual bandwidth may vary depending on specific hardware and software
implementations.
4.4
Power Management
4.4.1
Clock Control Architecture
The clock control architecture is optimal for low-power designs. The clock control architecture
consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant
Snoop, Sleep, and Deep Sleep states. The Auto Halt state provides a low-power clock state that can
be controlled through the software execution of the HLT instruction. The Quick Start state provides
a very low-power, low-exit latency clock state that can be used for hardware controlled “idle”
states. The Deep Sleep State provides an extremely low power state that can be used for “Power-on
Suspend” states, which is an alternative to shutting off the processor’s power. The exit latency of
the Deep Sleep State has been reduced to 30 μs. The Stop Grant and Sleep states are not available
on the module since these states are intended for desktop or server systems. The Stop Grant state
and the Quick Start clock state are mutually exclusive. For example, a strapping option on signal
A15# chooses which state is entered when the STPCLK# signal is asserted. Strapping the A15#
signal enables the Quick Start state to ground at Reset. Otherwise, asserting the STPCLK# signal
puts the processor into the Stop Grant state. The Stop Grant state is useful for SMP platforms and is
not supported on the module. The Quick Start state is available on the module and provides a
significantly lower power level.
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