![](http://datasheet.mmic.net.cn/330000/PM7382-PI_datasheet_16444416/PM7382-PI_28.png)
RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
17
Pin Name
Type
Pin
No.
Function
TD[0]
TD[1]
TD[2]
TD[3]
TD[4]
TD[5]
TD[6]
TD[7]
TD[8]
TD[9]
TD[10]
TD[11]
TD[12]
TD[13]
TD[14]
TD[15]
TD[16]
TD[17]
TD[18]
TD[19]
TD[20]
TD[21]
TD[22]
TD[23]
TD[24]
TD[25]
TD[26]
TD[27]
TD[28]
TD[29]
TD[30]
TD[31]
Output
W23
Y22
W20
AA22
Y20
AB23
AC22
AC21
AC20
AA19
AA18
AB18
Y17
AA17
AB16
AC15
AC14
AA14
AC13
AB13
AA12
AB11
Y11
AB10
Y9
AA8
AC8
AB7
AC7
AC6
AC5
AB4
The transmit data signals (TD[31:0]) contain the
transmit data for the 32 independently timed
links in normal mode (PMCTEST set low).
Processing of the transmit links is on a priority
basis, in descending order from TD[0] to TD[31].
Therefore, the highest rate link should be
connected to TD[0] and the lowest to TD[31].
For H-MVIP links, TD[n] contain 32/128 time-
slots, depending on the H-MVIP data rate
configured (2.048 or 8.192 Mbps). When
configured for 2.048 Mbps H-MVIP operation,
TD[31:24], TD[23:16], TD[15:8] and TD[7:0] are
updated on every 2
nd
falling edge of TMVCK[3],
TMVCK[2], TMVCK[1] and TMVCK[0]
respectively. When configured for 8.192 Mbps
H-MVIP operation, TD[4m] (0 m 7) are updated
on every 2
nd
falling edge of TMV8DC.
For channelised links, TD[n] contains the 24
(T1/J1) or 31 (E1) time-slots that comprise the
channelised link. TCLK[n] must be gapped
during the T1/J1 framing bit position or during
the E1 frame alignment signal (time-slot 0). The
FREEDM-32P256 uses the location of the gap
to determine the channel alignment on TD[n].
TD[31:0] are updated on the falling edge of the
corresponding TCLK[31:0].
For unchannelised links, TD[n] contains the
HDLC packet data. For certain transmission
formats, TD[n] may contain place holder bits or
time-slots. TCLK[n] must be externally gapped
during the place holder positions in the TD[n]
stream. The FREEDM-32P256 supports a
maximum data rate of 10 Mbit/s on an individual
TD[31:3] link and a maximum data rate of 51.84
Mbit/s on TD[2:0].
TD[31:0] are updated on the falling edge of the
corresponding TCLK[31:0] clock.