![](http://datasheet.mmic.net.cn/330000/PM7382-PI_datasheet_16444416/PM7382-PI_7.png)
RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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LIST OF FIGURES
FIGURE 1 – H-MVIP PROTOCOL ....................................................................36
FIGURE 2 – HDLC FRAME...............................................................................37
FIGURE 3 – CRC GENERATOR.......................................................................37
FIGURE 4 – PARTIAL PACKET BUFFER STRUCTURE..................................43
FIGURE 5 – RECEIVE PACKET DESCRIPTOR...............................................45
FIGURE 6 – RECEIVE PACKET DESCRIPTOR TABLE...................................48
FIGURE 7 – RPDRF AND RPDRR QUEUES ...................................................50
FIGURE 8 – RPDRR QUEUE OPERATION......................................................52
FIGURE 9 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........53
FIGURE 10 – GPIC ADDRESS MAP ................................................................60
FIGURE 11 – TRANSMIT DESCRIPTOR..........................................................62
FIGURE 12 – TRANSMIT DESCRIPTOR TABLE .............................................66
FIGURE 13 – TDRR AND TDRF QUEUES.......................................................68
FIGURE 14 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....70
FIGURE 15 – TD LINKING................................................................................73
FIGURE 16 – PARTIAL PACKET BUFFER STRUCTURE................................77
FIGURE 17 – INPUT OBSERVATION CELL (IN_CELL).................................277
FIGURE 18 – OUTPUT CELL (OUT_CELL) ...................................................278
FIGURE 19 – BI-DIRECTIONAL CELL (IO_CELL) .........................................278
FIGURE 20 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS
..............................................................................................................279
FIGURE 21 – BOUNDARY SCAN ARCHITECTURE......................................281
FIGURE 22 – TAP CONTROLLER FINITE STATE MACHINE........................283