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RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
18
Pin Name
Type
Pin
No.
Function
TMVCK[0]
TMVCK[1]
TMVCK[2]
TMVCK[3]
Input
V21
Y19
AA15
AB9
The transmit MVIP data clock signals
(TMVCK[3:0]) provide the transmit data clocks
for the 32 links when configured to operate in
2.048 Mbps H-MVIP mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common clock. TMVCK[0], TMVCK[1],
TMVCK[2] and TMVCK[3] update the data on
links TD[7:0], TD[15:8], TD[23:16] and TD[31:24]
respectively. Each TMVCK[n] is nominally a
50% duty cycle clock with a frequency of 4.096
MHz.
TMVCK[n] is ignored and should be tied low
when no physical link within the associated
group of 8 logical links is configured for
operation in 2.048 Mbps H-MVIP mode.
TFPB[0]
TFPB[1]
TFPB[2]
TFPB[3]
Input
V23
AA20
AB15
AA9
The transmit frame pulse signals (TFPB[3:0])
reference the beginning of each frame when
configured for operation in 2.048 Mbps H-MVIP
mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common frame pulse. TFPB[0], TFPB[1],
TFPB[2] and TFPB[3] reference the beginning of
a frame on links TD[7:0], TD[15:8], TD[23:16]
and TD[31:24] respectively.
When configured for operation in 2.048 Mbps H-
MVIP mode, TFPB[n] is sampled on the falling
edge of TMVCK[n]. Otherwise, TFPB[n] is
ignored and should be tied low.