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| 型號(hào)： | PM7383 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁(yè)數(shù)： | 114/231頁(yè) |
| 文件大小： | 1947K |
| 代理商： | PM7383 |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
106
Reserved:
The reserved bit must be set low for correct operation of the FREEDM-
32A256 device.
TAVAIL:
The indirect transaction available bit (TAVAIL) reports the fill level of the partial
packet buffer used in the logical FIFO of the current channel. TAVAIL is set
high when the FIFO of the current channel contains sufficient data, as
controlled by XFER[3:0], to result in a transfer across the receive APPI.
TAVAIL is set low when the amount of receive data is too small to result in a
transfer across the receive APPI. TAVAIL is updated by an indirect channel
read operation.
DELIN:
The indirect delineate enable bit (DELIN) configures the HDLC processor to
perform flag sequence delineation and bit de-stuffing on the incoming data
stream. The delineate enable bit to be written to the channel provision RAM,
in an indirect channel write operation, must be set up in this register before
triggering the write. When DELIN is set high, flag sequence delineation and
bit de-stuffing is performed on the incoming data stream. When DELIN is set
low, the HDLC processor does not perform any processing (flag sequence
delineation, bit de-stuffing nor CRC verification) on the incoming stream.
DELIN reflects the value written until the completion of a subsequent indirect
channel read operation.
STRIP:
The indirect frame check sequence discard bit (STRIP) configures the HDLC
processor to remove the CRC from the incoming frame when writing the data
to the channel FIFO. The FCS discard bit to be written to the channel
provision RAM, in an indirect channel write operation, must be set up in this
register before triggering the write. When STRIP is set high and CRC[1:0] is
not equal to “00”, the received CRC value is not written to the FIFO. When
STRIP is set low, the received CRC value is written to the FIFO. The bytes in
buffer field of the RPD correctly reflect the presence/absence of CRC bytes in
the buffer. The value of STRIP is ignored when DELIN is low. STRIP reflects
the value written until the completion of a subsequent indirect channel read
operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the channel provision RAM after an indirect channel read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM7383-PI | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| PM7384 | Frame Engine and Data Link Manager |
| PM7384-BI | FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | Frame Engine and Data Link Manager |
| PM7385-BI | 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7383-PI | 制造商:PMC 制造商全稱(chēng):PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| PM7384 | 制造商:PMC 制造商全稱(chēng):PMC 功能描述:Frame Engine and Data Link Manager |
| PM7384-BI | 制造商:PMC 制造商全稱(chēng):PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 84P672 |
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