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參數(shù)資料
| 型號(hào)： | PM7383 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁(yè)數(shù)： | 56/231頁(yè) |
| 文件大?。?/td> | 1947K |
| 代理商： | PM7383 |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
48
When a link is configured for operation in H-MVIP mode, the LIT block samples
the appropriate frame pulse (RFPB[n] for 2.048 Mbps H-MVIP and RFP8B for
8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the gapped clock is passed to the LIT block unmodified.
8.3.2 Line Interface
There are 32 identical line interface blocks in the RCAS256. Each line interface
block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and
the other H-MVIP streams. Based on configuration, only one of the sub-blocks
are active at one time; the other is held reset. Each sub-block contains a bit
counter, an 8-bit shift register and a holding register. Each sub-block performs
serial to parallel conversion. Whenever the holding register is updated, a request
for service is sent to the priority encoder block. When acknowledged by the
priority encoder, the line interface would respond with the data residing in the
holding register in the active sub-block.
To support H-MVIP links, each line interface block contains a time-slot counter.
The time-slot counter is incremented each time the holding register is updated.
When a frame pulse occurs, the time-slot counter is initialised to indicate that the
next bit is the most significant bit of the first time-slot.
To support non H-MVIP channelised links, each line interface block contains a
time-slot counter and a clock activity monitor. The time-slot counter is
incremented each time the holding register is updated. The clock activity monitor
is a counter that increments at the system clock (SYSCLK) rate and is cleared by
a rising edge of the receive clock (RCLK[n]). A framing bit (T1/J1) or a framing
byte (E1) is detected when the counter reaches a programmable threshold, in
which case, the bit and time-slot counters are initialised to indicate that the next
bit is the most significant bit of the first time-slot. For unchannelised links, the
time-slot counter and the clock activity monitor are held reset.
8.3.3 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from the line interface
attached to RD[0] to that attached to RD[31]. Thus, simultaneous requests from
RD[m] will be serviced ahead of RD[n], if m < n. When there are no pending
requests, the priority encoder generates an idle cycle. In addition, once every
fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM7383-PI | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| PM7384 | Frame Engine and Data Link Manager |
| PM7384-BI | FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | Frame Engine and Data Link Manager |
| PM7385-BI | 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7383-PI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| PM7384 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
| PM7384-BI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 84P672 |
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