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| 型號： | POE-VOICE-RD |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 33/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT REF DESIGN PWR OVER ETHERNET |
| 標準包裝： | 1 |
| 主要目的： | 參考設(shè)計，以太網(wǎng)供電（POE），語音傳輸 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | C8051F340，CP2201，Si3400 |
| 主要屬性： | 嵌入式以太網(wǎng)，以太網(wǎng)供電，8 kHz 語音采樣系統(tǒng) |
| 次要屬性： | 圖形用戶界面 |
| 已供物品： | 板，線纜，電源，軟件 |
| 產(chǎn)品目錄頁面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 336-1385-ND - IC POWER OVER ETHERNET 20QFN 336-1322-ND - IC POWER OVER ETHERNET 20QFN 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN 336-1298-ND - IC 8051 MCU FLASH 64K 48TQFP |
| 其它名稱： | 336-1326 |
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CP2200/1
30
Rev. 1.0
8. Interrupt Sources
The CP2200/1 can alert the host processor when any of the 14 interrupt source events listed in Table 12 triggers
an interrupt. The CP2200/1 alerts the host by setting the appropriate flags in the interrupt status registers and
driving the INT pin low. The INT pin will remain asserted until all interrupt flags for enabled interrupts have been
cleared by the host. Interrupt flags are cleared by reading the self-clearing interrupt status registers, INT0 and
INT1. Interrupts can be disabled by clearing the corresponding bits in INT0EN and INT1EN.
If the host processor does not utilize the INT pin, it can periodically read the interrupt status registers to determine
if any interrupt-generating events have occurred. The INT0RD and INT1RD read-only registers provide a method
of checking for interrupts without clearing the interrupt status registers.
Table 12. Interrupt Source Events
Event
Description
Pending
Flag
Enable
Flag
End of Packet
The last byte of a packet has been read from the
receive buffer using the AutoRead interface.
INT0.7
INT0EN.7
Receive FIFO Empty
The last packet in the receive buffer has been unloaded
or discarded.
INT0.6
INT0EN.6
Self Initialization Complete
The device is ready for Reset Initialization. See “6.2.
INT0.5
INT0EN.5
Oscillator Initialization Complete The external oscillator has stabilized.
INT0.4
INT0EN.4
Flash Write/Erase Complete
A Flash write or erase operation has completed.
INT0.3
INT0EN.3
Packet Transmitted
The transmit interface has transmitted a packet.
INT0.2
INT0EN.2
Receive FIFO Full
The receive buffer is full or the maximum number of
packets has been exceeded. Decode the RXFIFOSTA
status register to determine the receive buffer status.
INT0.1
INT0EN.1
Packet Received
A packet has been added to the receive buffer.
INT0.0
INT0EN.0
“Wake-on-LAN” Wakeup Event
The device has been connected to a network.
INT1.5
INT1EN.5
Link Status Changed
The device has been connected or disconnected from
the network.
INT1.4
INT1EN.4
Jabber Detected
The transmit interface has detected and responded to a
jabber condition. See IEEE 802.3 for more information
about jabber conditions.
INT1.3
INT1EN.3
Auto-Negotiation Failed
An auto-negotiation attempt has failed. Software should
check for a valid link and re-try auto-negotiation.
INT1.2
INT1EN.2
Reserved
Auto-Negotiation Complete
An auto-negotiation attempt has completed. This inter-
rupt only indicates completion, and not success. Occa-
sionally, Auto-Negotiation attempts will not complete
and/or fail; therefore, a 3 to 4 second timeout should be
implemented. A successful auto-negotiation attempt is
one that completes without failure.
INT1.0
INT1EN.0
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