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參數(shù)資料
| 型號： | POE-VOICE-RD |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 67/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT REF DESIGN PWR OVER ETHERNET |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 參考設(shè)計，以太網(wǎng)供電（POE），語音傳輸 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | C8051F340，CP2201，Si3400 |
| 主要屬性： | 嵌入式以太網(wǎng)，以太網(wǎng)供電，8 kHz 語音采樣系統(tǒng) |
| 次要屬性： | 圖形用戶界面 |
| 已供物品： | 板，線纜，電源，軟件 |
| 產(chǎn)品目錄頁面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 336-1385-ND - IC POWER OVER ETHERNET 20QFN 336-1322-ND - IC POWER OVER ETHERNET 20QFN 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN 336-1298-ND - IC 8051 MCU FLASH 64K 48TQFP |
| 其它名稱： | 336-1326 |
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CP2200/1
Rev. 1.0
61
Register 34. RXCN: Receive Interface Control
Register 35. RXSTA: Receive Interface Status
Bits 7–4: UNUSED. Read = 0000b, Write = don’t care.
Bit 3:
RXINH: Receive Inhibit
Setting this bit to ‘1’ temporarily inhibits new packet reception. If a packet is currently being
received, reception will continue until the packet is received. Once set, this bit must be cleared to ‘0’
by software to resume packet reception.
Bit 2:
RXCLRV: Valid Bit Clear
Writing a ‘1’ to this bit clears the valid bit of the current packet, freeing up the buffer for new packets.
This action should only be started after all bytes of the current packet have been read (CPEND = 1).
If the packet is not completely read, RXSKIP should be used to discard the remaining bytes.
Bit 1:
RXSKIP: Skip Current Packet
Writing a ‘1’ to this bit updates discards the current packet by clearing its valid bit and advances the
AutoRead buffer pointer to the beginning of the next packet.
Bit 0:
RXCLEAR: Receive Buffer Clear
Writing a ‘1’ to this bit discards all packets in the receive buffer and resets all buffer pointers and
valid bits to zero. Note: Any packets currently in the buffer will remain in memory, however, all infor-
mation such as the starting address and length of each packet will be lost. Any new packets that
arrive will overwrite the existing data.
R/W
W
Reset Value
—
RXINH
RXCLRV
RXSKIP RXCLEAR 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x11
Bits 7–2: UNUSED. Read = 000000b, Write = don’t care.
Bit 1:
CPEND: Current Packet End Reached
This bit is automatically cleared by hardware when the valid bit for the current packet is cleared (see
RXCLRV description) or the current packet is discarded (see RXSKIP description).
0: The last byte of the current packet has not been read using the AutoRead interface.
1: The last byte of the current packet has been read using the AutoRead interface.
Bit 0:
RXBUSY: Receiving Packet
0: Receive interface is idle.
1: Receive interface is currently receiving a packet.
R/WR/WR/WR/WR/WR/W
R
Reset Value
—
CPEND
RXBUSY 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x12
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