參數(shù)資料
型號(hào)： POE-VOICE-RD
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 48/108頁(yè)
文件大?。?/td> 0K
描述： KIT REF DESIGN PWR OVER ETHERNET
標(biāo)準(zhǔn)包裝： 1
主要目的： 參考設(shè)計(jì)，以太網(wǎng)供電（POE），語(yǔ)音傳輸
嵌入式： 是，MCU，8 位
已用 IC / 零件： C8051F340，CP2201，Si3400
主要屬性： 嵌入式以太網(wǎng)，以太網(wǎng)供電，8 kHz 語(yǔ)音采樣系統(tǒng)
次要屬性： 圖形用戶(hù)界面
已供物品： 板，線(xiàn)纜，電源，軟件
產(chǎn)品目錄頁(yè)面： 626 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 336-1385-ND - IC POWER OVER ETHERNET 20QFN
336-1322-ND - IC POWER OVER ETHERNET 20QFN
336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN
336-1298-ND - IC 8051 MCU FLASH 64K 48TQFP
其它名稱(chēng)： 336-1326
CP2200/1
44
Rev. 1.0
10.1. Normal Mode
Normal Mode should is used whenever the host is sending or receiving packets. In this mode, the CP2200/01 is
fully functional. Typical Normal Mode power consumption is listed in Table 2 on page 9.
Note: When in normal mode, the transmitter has a power saving mode which is enabled on reset. This power saving mode dis-
ables the transmitter's output driver and placed the TX+/- pins in high impedance when the CP220x is not transmitting
link pulses or data. To meet the minimum transmitter loss requirements in IEEE 802.3, this power saving mode should be
10.2. Link Detection Mode
In Link Detection Mode, the transmitter and link pulse generation logic is disabled. The CP2200/1 will appear to be
“offline” because link pulses will not be generated. The most common way to use Link Detection Mode is enabling
the Wake-on-LAN interrupt, placing the CP2200/01 into Link Detection Mode, then placing the MCU in a low power
mode until the system is plugged into a network.
Note: When using link detection mode, the user should ensure that the link partner is always transmitting link pulses. An exam-
ple of this type of device would be a hub or a switch. Some notebook PCs implement a power saving feature in which
they stop transmitting link pulses if a valid link is not detected. This would create a situation where both link partners are
waiting for each other to start transmitting link pulses.
Note: A minimum transmitter return loss is specified in IEEE 802.3. If the transmitter is disabled, the TX± pins are placed in
high impedance mode and do not create the minimum return loss. The transmitter should not be disabled if the device is
considered "on a network" and valid link pulses are being received.
From Normal Mode, the device can be placed in Link Detection Mode by clearing TXEN (PHYCN.6) to “0”. To
return the device to Normal Mode, disable the physical layer by clearing PHYCN to 0x00, then re-enable the
physical layer using the startup procedure in Section 15.7 on page 90.
10.3. Memory Mode
In Memory Mode, the physical layer (receiver and transmitter) is placed in a low-power state, and the CP2200/1
can neither send nor receive packets. The only primary functions of the device that remain functional are the Flash
memory and RAM buffers. The RAM buffers are only accessible using the Random Access method described in
The device can be placed in Memory Mode by clearing the three most significant bits of the PHYCN register to
‘000’. The device can be returned to normal mode by setting the three most significant bits of the PHYCN register
to ‘111’ and waiting the appropriate physical layer turn-on times for both the transmitter and the receiver. The
physical layer electrical characteristics including turn-on time are specified in Table 22 on page 93. To return the
device to Normal Mode, disable the physical layer by clearing PHYCN to 0x00, then re-enable the physical layer
using the startup procedure in Section 15.7 on page 90.
10.4. Shutdown Mode
Shutdown Mode is the lowest power mode for the CP2200/1. All primary and secondary functions are disabled,
and the system clock is disconnected from the oscillator. The device can recover from Shutdown Mode only
through a power-on or pin reset.
The device can be placed in Shutdown Mode using the following procedure:
Step 1: Disable the PHY by clearing the three most significant bits of PHYCN to ‘000’.
Step 2: Disable the LED drivers by clearing bits 2 and 3 of IOPWR to ‘00’.
Step 3: Disable the VDD Monitor (optional) by clearing VDMEN (VDMCN.7) to ‘0’.
Step 4: Disconnect the oscillator output from the rest of the device by clearing OSCOE (OSCPWR.0) to ‘0’.
This step should be performed last because the device will no longer respond until the next pin or
power-on reset.
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