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參數(shù)資料
| 型號： | PSD301L |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有12個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，19余個可編程輸入/輸出，通用PLD的有12個輸入） |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 118K |
| 代理商： | PSD301L |
3-24
Flash Memory – Application Note 048
80C31 Example
(cont.)
The detailed solution using a PSD311 is shown in Figure 4. The required logic equations
are shown in Table 2. When the 80C31 writes a logical “1” to the Program Bit (Port 1, bit 0
on the 80C31), the memory map is switched from the Operational Mode to the
Programming Mode as show in Figures 2 and 3. The latched address (A0–7) appears on
Port A. Port B provides the control signals along with the upper address lines for the Flash
Memory. Controlling the upper two address lines of the Flash Memory allows the PSD to
map each 16 Kbytes of Flash Memory anywhere in the 64 Kbyte address space and on any
page of the memory map. Since the PSD311 does not have a built-in page register (the
PSD312 device has a 4-bit page register), three I/O port pins on the 80C31 are used as a 3-
bit page register. These signals are routed into the PLD inside the PSD311. Another way to
implement the page register in the PSD311 is to use PB0–2 as output pins instead of using
the I/O pins on the 80C31. These pins are routed back to the PSD311 through Port C and
A19 in the same manner as shown in Figure 4. Note that the PSEN signal is connected to
PC2. This will route the PSEN signal into PAD B (or GPLD) for external chip selects. The
PSDabel file along with the Fitter Report are shown in Appendix A.
EA/VP
X1
X2
INT0
INT1
T0
T1
P1 1–7
TXD
RXD
P0 0–7
AD0–7/A0–7
AD8–15/A8–15
RD
WR
PSEN
ALE
PC2
A16
A15
A8–A14
A0–7
FLASH_OE
FLASH_WR
FLASH_CS
RESET
A19/CSI
PC0
PC1
PB7
D0–7
PB6
PB5
PA0–7
PB4
PB3
PB0–2
P2 0–7
RD
WR
PSEN
ALE/P
RESET
PROGRAM
MCU PGR0
MCU PGR1
RESET
*
P1 0
P1 1
P1 2
80C31/51
PSD311
EXT. FLASH
MEMORY
ADDRESS
ADDRESS/
DATA
Figure 4. PSD311 with External Flash Memory
DPLD Equations
rs0
= (address > =
^
h0800) & (address < =
^
h0FFF);
es0
= (address > =
^
h0000) & (address < =
^
h0FFF);
es1
= (address > =
^
h1000) & (address < =
^
h1FFF);
es2
= (address > =
^
h2000) & (address < =
^
h2FFF);
es3
= (address > =
^
h3000) & (address < =
^
h3FFF);
csiop = (address > =
^
h0000) & (address < =
^
h07FF);
GPLD Equations
Flash_A16
Flash_A15
Flash_OE
Flash_WR
Flash_CS
= a15 & ((page = = 1) # (page = = 2));
= a15 & ((page = = 0) # (page = = 2));
= !((!program & !psen) # (program & !rd));
= !(program & !wr);
= !((address > =
^
h4000) & (address < =
^
hFFFF));
Table 2. Logic Equations for the PSD311
*RESET Signal. The external reset must have a fast rise time from a logic gate, not a slow rise time generated
from an RC circuit.
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| PSD302R | Field Programmable Microcontroller Peripherals(可編程邏輯,無SRAM,19個可編程I/O,通用PLD有16個輸入) |
| PSD303L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入) |
| PSD303 | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入) |
| PSD311L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有12個輸入) |
| PSD311 | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有12個輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD301L-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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