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參數(shù)資料
| 型號(hào)： | PSD301L |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有12個(gè)輸入） |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 118K |
| 代理商： | PSD301L |
Flash Memory – Application Note 048
3-25
The detailed solution using a PSD411A1 is shown in Figure 5. The PSD411A2 or
PSD511B1 can also be used in this example. The required logic equations are shown in
Table 3. When the Microcontroller writes a logical “1” to the Page Register Bit 3 at address
location
^
h0018 (CSIOP +
^
h18), the memory map is switched from the Operational
Mode to the Programming Mode as shown in Figures 2 and 3. This Page Register is
reset to zero when a Reset occurs on the PSD. The latched address (A0–7) appears on
Port D. This must be initialized by writing a
^
hFF to the Directional Register on Port D
(CSIOP +
^
h16). Port A provides the control signals along with the upper address lines for
the Flash Memory. The PSDabel file along with the Fitter Report are shown in Appendix B.
Note that CSIOP =
^
h00 in the above two examples (see the definition of CSIOP in the
PSDabel file shown in corresponding appendixes).
80C31 Example
(cont.)
EA/VP
X1
X2
INT0
INT1
T0
T1
P1 0–7
TXD
RXD
P0 0–7
AD0–7/A0–7
AD8–15/A8–15
RD
WR
PE0/PSEN
PE1/ALE
A16
A15
A8–A14
A0–7
FLASH_OE
FLASH_WR
FLASH_CS
PE2
RESET
CLKIN
CSI
VSTDBY
PA4
D0–7
PA3
PA2
PD0–7
PA1
PA0
PA5–7
PB0–7
PC0–7
PE3–7
P2 0–7
RD
WR
PSEN
ALE/P
RESET
RESET OUT
RESET
80C31/51
PSD411/511
EXT. FLASH
MEMORY
CLOCK
ADDRESS
DATA
ADDRESS
ADDRESS/
DATA
*
Figure 5. PSD411/511 with External Flash Memory
*RESET OUT Signal is optional. An external reset can be used to make Port Pin PE2 available for other use.
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| PSD302R | Field Programmable Microcontroller Peripherals(可編程邏輯,無SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD303L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
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| PSD311 | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD301L-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD301L-15U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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