參數資料
型號： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁數： 17/98頁
文件大小： 595K
代理商： PSD834F2
17/98
PSD8XXF2/3/4/5
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD8xxF2/3/4/5 and not executed
as a standard Write operation. The instruction is
executed when the correct number of bytes are
properly received and the time between two con-
secutive bytes is shorter than the time-out period.
Some instructions are structured to include Read
operations after the initial Write operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).
The PSD8xxF2/3/4/5 supports the instructions
summarized in Table 8:
Flash memory:
I
Erase memory by chip or sector
I
Suspend or resume sector erase
I
Program a Byte
I
Reset to Read mode
I
Read primary Flash Identifier value
I
Read Sector Protection Status
I
Bypass (on the PSD833F2, PSD834F2,
PSD853F2 and PSD854F2)
These instructions are detailed in Table 8. For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy-
cle. Address signals A15-A12 are Don’t Care dur-
ing the instruction Write cycles. However, the
appropriate
Sector
Select
CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memoryis selected
if
any
one
of
Sector
CSBOOT3) is High.
Power-down Instruction and Power-up Mode
Power-up Mode.
The PSD8xxF2/3/4/5 internal
logic is reset upon Power-up to the Read mode.
Sector
Select
(FS0-FS7
CSBOOT3) must be held Low, and Write Strobe
(WR, CNTL0)High, during Power-up for maximum
security of the data contents and to remove the
possibility of a byte being written on the first edge
(FS0-FS7
or
Select
(CSBOOT0-
and
CSBOOT0-
of Write Strobe (WR, CNTL0). Any Write cycle ini-
tiation is locked when V
CC
is below V
LKO
.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using Read operations just as it would a
ROM or RAM device. Alternately, the MCU may
use Read operations to obtain status information
about a Program or Erase cycle that is currentlyin
progress. Lastly, theMCU mayuse instructions to
read special data from these memory blocks. The
following sections describe these Read functions.
Read Memory Contents.
Primary Flash memory
and secondary Flash memory are placed in the
Read mode after Power-up, chip reset, or a Reset
Flash instruction(see Table8). The MCU can read
the memory contents of the primary Flash memory
or the secondaryFlash memory by using Read op-
erations any time the Read operation is not part of
an instruction.
Read Primary Flash Identifier.
The
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific Write opera-
tions and a Read operation (see Table 8). During
the Read operation, address bits A6, A1, and A0
must be 0,0,1, respectively, and the appropriate
Sector Select (FS0-FS7) must be High. The iden-
tifier for the PSD813F2/3/4/5 is E4h, and for the
PSD83xF2 or PSD85xF2 it is E7h.
Read Memory Sector Protection Status.
The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific Write operations and a Read operation
(see Table8). Duringthe Read operation,address
bits A6, A1, and A0 must be 0,1,0, respectively,
while Sector Select (FS0-FS7 or CSBOOT0-
CSBOOT3) designates the Flash memory sector
whose protection has to be verified. The Read op-
eration produces 01h if theFlash memory sector is
protected, or 00h if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled “Flash Memory Sector Pro-
tect”, on page 22, for register definitions.
Reading the Erase/Program Status Bits.
The
PSD8xxF2/3/4/5 provides several status bits to be
used by the MCU to confirm the completion of an
Erase or Program cycle of Flash memory. These
status bits minimize the timethat theMCU spends
performing these tasks and are defined inTable 9.
The status bits can be read as many times as
needed.
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
primary
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相關代理商/技術參數
參數描述
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
PSD834F2-70J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-70M 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD834F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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