參數(shù)資料
型號： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁數(shù)： 61/98頁
文件大?。?/td> 595K
代理商： PSD834F2
61/98
PSD8XXF2/3/4/5
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface block can be enabled
on Port C (see Table 34). All memory blocks (pri-
mary and secondary Flash memory), PLD logic,
and PSD8xxF2/3/4/5 Configuration Register bits
may be programmed through the JTAG Serial In-
terface block. A blank device can be mounted on
a printed circuit board and programmed using
JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Twoadditional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank PSD8xxF2/3/4/5 (as
shipped from the factory or after erasure), four
pins onPort C are enabled for thebasic JTAG sig-
nals TMS, TCK, TDI, and TDO.
See Application Note AN1153 for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) canbe enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
JTAG serial command froman external JTAGcon-
troller device (such as FlashLINK or Automated
Test Equipment). When the enabling command is
received, TDO becomes an output and the JTAG
channel is fully functional inside the PSD8xxF2/3/
4/5. The same command that enables the JTAG
channel may optionally enable the two additional
JTAG signals, TSTAT and TERR.
The following symbolic logic equationspecifies the
conditions enabling the four basic JTAG signals
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD8xxF2/3/4/5 I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the
PSD
is
set
by
the
designer
PSDsoft Express Configuration utility.
This dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1 */
Microcontroller_enabled
+
/* The microcontroller can set a bit at
run-time
by
writing
to
register,
JTAG
Enable.
This register
is located at address CSIOP + offset
C7h.
Setting
the
JTAG_ENABLE
this register will enable the pins for
JTAG use. This bit is cleared by a PSD
reset
or
the
microcontroller.
Table 35 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside
the PSD can be used to enable the JTAG
pins.
This
PT
has
the
reserved
in
the
the
PSD
bit
in
See
name
JTAGSEL.
PSDabel,
equation
used
multiplexed with other I/O signals. It
is
recommended
to
node JTAGSEL to the JEN\ signal on the
Flashlink cable when multiplexing JTAG
signals. See Application Note 1153 for
details. */
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM configuration
bit (via PSDsoft Express). However, Reset (RE-
SET) will prevent or interrupt JTAG operations if
the JTAG enable register is used to enable the
JTAG pins.
The PSD8xxF2/3/4/5 supports JTAG In-System-
Configuration (ISC) commands, but not Boundary
Scan. The PSDsoft Express software tool and
FlashLINK JTAG programming cable implement
the JTAG In-System-Configuration (ISC) com-
mands. A definition of these JTAG In-System-
Configuration (ISC) commands and sequences is
defined in a supplemental document available
from ST. Thisdocument isneeded only as a refer-
ence for designers who use a FlashLINK to pro-
gram their PSD8xxF2/3/4/5.
Once
the
for JTAGSEL.
when
the
defined
designer
as
can
This method is
JTAG
pins
a
node
write
in
an
Port
C
are
logically
tie
the
Table 34. JTAG Port Signals
JTAG Extensions
TSTAT and TERR aretwoJTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and
Erase
cycles
by
PSD8xxF2/3/4/5 signals instead of having to scan
the status out serially using the standard JTAG
channel. See Application Note AN1153
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set
(RESET)
pulse
“ISC_DISABLE” command.
indicating
status
on
is
received
after
an
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
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相關代理商/技術參數(shù)
參數(shù)描述
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
PSD834F2-70J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-70M 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD834F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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