參數(shù)資料
型號： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁數(shù)： 47/98頁
文件大?。?/td> 595K
代理商： PSD834F2
47/98
PSD8XXF2/3/4/5
Table 21. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in thePSDabelfile, then theDirection Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the InputMacrocells (IMC) drive thePLD input bus
and can be read by the MCU. See the section en-
titled “Input Macrocell”, on page 35.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Control Registers
in CSIOP space, and some by both. The modes
that can only be defined using PSDsoft Express
must be programmed into the device and cannot
be changed unless the device is reprogrammed.
The modes that can be changed by the MCU can
be done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, and Peripheral I/O
modes are the only modes that must be defined
before programming the device. All other modes
can be changed by the MCU at run-time. See Ap-
plication Note AN1171 for more detail.
Table 19 summarizes which modes are available
on each port. Table 22 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In the MCU I/O mode, theMCU uses the I/O Ports
block toexpand itsown I/O ports.By setting up the
CSIOP space, the ports on the PSD8xxF2/3/4/5
are mapped into the MCU address space. The ad-
dresses of the ports are listed in Table 7.
A port pin canbe putinto MCU I/O modeby writing
a 0 to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled “Peripheral I/O Mode”, on
page 48. When the pin is configured as an output,
the contentof the DataOut Register drives thepin.
When configured as an input, the MCU can read
the port input through the Data In buffer. See Fig-
ure 23.
Ports C and D do not have Control Registers, and
are in MCU I/O modeby default. Theycan be used
for PLD I/O if equations are written for them inPS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from thePLD, or by resetting the
corresponding bit in the Direction Register to 0.
The corresponding bit in the Direction Register
must not be set to 1 if the pin is defined for a PLD
input signal in PSDabel. The PLD I/O mode is
specified in PSDabel by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Address Out Mode
For MCUs with a multiplexed address/data bus,
Address Out Mode can be used to drive latched
addresses on tothe portpins. Theseport pins can,
in turn, drive external devices. Either the output
enable orthe corresponding bits of both the Direc-
tion Register and Control Register must be set to
a 1 for pins to use Address Out Mode. This must
be done by the MCU at run-time. See Table 21 for
the address output pin assignments on Ports A
and B for various MCUs.
Port A (PA3-PA0)
Port A (PA7-PA4)
Port B (PB3-PB0)
Port B (PB7-PB4)
8051XA (8-Bit)
N/A
1
Address a7-a4
Address a11-a8
N/A
80C251
(Page Mode)
N/A
N/A
Address a11-a8
Address a15-a12
All Other
8-Bit Multiplexed
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
8-Bit
Non-Multiplexed Bus
N/A
N/A
Address a3-a0
Address a7-a4
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