參數(shù)資料
型號(hào)： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁(yè)數(shù)： 19/98頁(yè)
文件大?。?/td> 595K
代理商： PSD834F2
19/98
PSD8XXF2/3/4/5
Programming Flash Memory
Flash memory must be erased prior to being pro-
grammed. A byte of Flash memory is erased to all
1s (FFh), and is programmed by setting selected
bits to 0. The MCU may erase Flash memory all at
once or by-sector, but not byte-by-byte. However,
the MCU may program Flash memory byte-by-
byte.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 8).
Once theMCU issues a Flash memoryProgram or
Erase instruction, it must check for the status bits
for completion. Theembedded algorithms that are
invoked inside the PSD8xxF2/3/4/5support sever-
al means to provide statusto theMCU. Status may
be checked using any of three methods: DataPoll-
ing, Data Toggle, or Ready/Busy (PC3).
Data Polling.
Polling on the Data Polling Flag
(DQ7) bit is a method of checking whether a Pro-
gram orErase cycle is in progress or has complet-
ed. Figure 4 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD8xxF2/3/4/5
begins. The MCU then reads the location of the
byte to be programmed in Flash memory to check
status. The Data Polling Flag (DQ7) bit of this lo-
cation becomes the complement of b7 of the orig-
inal data byte to be programmed. The MCU
continues to poll this location, comparing the Data
Polling Flag (DQ7) bit and monitoring the Error
Flag (DQ5)bit. When the Data Polling Flag (DQ7)
bit matches b7 of the original data, and the Error
Flag (DQ5) bit remains 0, the embedded algorithm
is complete. If the Error Flag (DQ5) bit is 1, the
MCU should test the Data Polling Flag (DQ7) bit
again since the Data Polling Flag (DQ7) bit may
have changed simultaneously with the Error Flag
(DQ5) bit (see Figure 4).
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted toprogram a 1 to a bit that was not erased
(not erased is logic 0).
It issuggested (as withall Flash memories)to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to the Flash memory with the
byte that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 4 still applies. However, the
Data Polling Flag (DQ7) bit is 0 until the Erase cy-
cle is complete. A 1 on the Error Flag (DQ5) bit in-
dicates a time-out condition on the Erase cycle; a
0 indicates no error. The MCU can read any loca-
tion within the sector being erased to get the Data
Polling Flag (DQ7) bit andthe Error Flag (DQ5)bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Polling algo-
rithms.
Figure 4. Data Polling Flowchart
Data Toggle.
Checking the Toggle Flag (DQ6) bit
is a method of determining whether a Program or
Erase cycle is in progress or has completed. Fig-
ure 5 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD8xxF2/3/4/5
begins. The MCU then reads the location of the
byte to beprogrammed in Flash memory to check
status. The Toggle Flag (DQ6) bit of this location
toggles eachtime theMCU reads this location until
the embedded algorithm is complete. The MCU
continues to read this location, checking the Tog-
gle Flag (DQ6) bit and monitoring the Error Flag
(DQ5) bit. When the Toggle Flag (DQ6) bit stops
toggling (two consecutive reads yield the same
value), and the Error Flag (DQ5) bit remains 0, the
embedded algorithm is complete. If the Error Flag
(DQ5) bit is 1, the MCU should test the Toggle
Flag (DQ6) bit again, since the Toggle Flag (DQ6)
bit may have changed simultaneously with the Er-
ror Flag (DQ5) bit (see Figure 5).
READ DQ5 &
DQ7
at VALID ADDRESS
START
READ DQ7
FAIL
PASS
AI01369B
DQ7
DATA
YES
NO
YES
NO
DQ5
= 1
DQ7
DATA
YES
NO
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PSD834F2-70J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-70M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD834F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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