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參數(shù)資料
| 型號(hào)： | Q67103-H6594 |
| 廠商： | SIEMENS AG |
| 英文描述： | Memory Time Switch Extended Large MTSXL |
| 中文描述： | 內(nèi)存定時(shí)開關(guān)擴(kuò)展大型MTSXL |
| 文件頁(yè)數(shù)： | 12/51頁(yè) |
| 文件大小： | 1052K |
| 代理商： | Q67103-H6594 |
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PEB 2447
Functional Description
Semiconductor Group
12
03.97
Figure 3
Block Diagram of MTSXL
The synchronization of the input and output counters is achieved by a rising edge of the
sync pulse SP, which is always sampled with the falling edge of the device clock.
Different modes of operation are configurable at the PCM interfaces (see
table 9
).
Furthermore, 16 PCM input lines can be aligned with individual clock shift values to
compensate different line delays. If 32 inputs are used, one clock shift value controls two
ports at the same time.
Shifting of the output frame is also possible, but all output lines are affected the same
way.
The input lines FS0 to FS5 are used as frame measurement inputs. After synchronizing
the device by the SP pulse the FS inputs can be evaluated on a per port basis. This
evaluation procedure is started by a microprocessor command. As a result the input
counter value on the rising edge of the FS signal can be read from an internal register.
Thus delay compensation is easily managed by programming appropriate clock shift
values and/or a possible software offset.
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