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參數(shù)資料
| 型號： | Q67103-H6594 |
| 廠商： | SIEMENS AG |
| 英文描述： | Memory Time Switch Extended Large MTSXL |
| 中文描述： | 內(nèi)存定時開關(guān)擴(kuò)展大型MTSXL |
| 文件頁數(shù)： | 41/51頁 |
| 文件大?。?/td> | 1052K |
| 代理商： | Q67103-H6594 |
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PEB 2447
Detailed Register Description
Semiconductor Group
41
03.97
4.13
Access in demultiplexed
μ
P-interface mode:
Read/write, address:
Reset value:
Input Clock Shift Register Bank ICSR (15:0)
10
H
...
1F
H
00
H
ADSR
Add Shift Register
; a three bit shift register is inserted into the
corresponding input(s), resulting in an additional offset for that/those
input(s). The sampling point is shifted
“backwards” by 3 clock cycles
(see
figure 9
).
Note:
ADSR has to be set to “0” in modes 1 and 3.
ICS4..0
Input Clock Shift; the value of ICS4..0 determines the number of
clock cycles by which the bit sampling point is shifted forward in all
input modes according to
figure 9
.
Receive
on
Rising Edge
; the PCM data of the corresponding
input(s) is sampled with the rising edge of the clock, if this bit is set.
These 16 registers determine the individual clock shift of inputs IN0 to IN15.
If more than sixteen inputs are used, two inputs are controlled by one ICSR register:
ICSR0
controls
IN0, IN8
ICSR1
”
IN1, IN9
ICSR2
”
IN2, IN10
.
.
.
.
ICSR7
”
IN7, IN15
ICSR8
”
IN16, IN24
ICSR9
”
IN17, IN25
ICSR10
”
IN18, IN16
.
.
.
.
ICSR15
”
IN23, IN31
The values of ICSR (15:0) can be adjusted without producing bit errors:
– clockrate = 2
×
datarate
possible adjustment is one half clock period forward or backward.
– clockrate = 4
×
datarate
possible adjustment is one clock period backward or two clock periods forward.
RRE
Bit 7
Bit 0
ADRS
0
ICS4
ICS3
ICS2
ICS1
ICS0
RRE
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