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參數(shù)資料
| 型號： | Q67103-H6594 |
| 廠商： | SIEMENS AG |
| 英文描述： | Memory Time Switch Extended Large MTSXL |
| 中文描述： | 內(nèi)存定時開關擴展大型MTSXL |
| 文件頁數(shù)： | 43/51頁 |
| 文件大?。?/td> | 1052K |
| 代理商： | Q67103-H6594 |
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PEB 2447
Detailed Register Description
Semiconductor Group
43
03.97
4.16
Access in a demultiplexed
μ
P-interface mode:
Read, address:
Reset value:
Frame Evaluation Register Low (FERL)
0E
H
XX
H
FEV7..0
Frame Evaluation Values
(bits 7 to 0); refer to FERH;
4.17
Access in demultiplexed
μ
P-interface mode:
Read, address:
Reset value:
Frame Evaluation Register High (FERH)
0F
H
XX
H
FEV11..0
Frame Evaluation Values
; after a frame evaluation procedure
(interrupt ISTA:FEC) these two registers contain the offset between
the SP frame and an evaluated FS0 ... FS5 frame. The evaluation is
performed at the second following rising edge of FS after the
command CMDR:SFE = 1 was programmed.
Note: The device must be synchronized to SP (STAR: PSS = 1) in
order to generate a correct result in FERL / FERH.
Note: Time constant
“X” is specified to 0 ns < X < 13 ns (see
figure 8
)
Bit 7
Bit 0
FEV7
FEV6
FEV5
FEV4
FEV3
FEV2
FEV1
FEV0
Bit 7
Bit 0
0
0
0
0
FEV11 FEV10
FEV9
FEV8
Table 15
Frame Evaluation Register
CLK / 1.024 MHz
16
Offset Value = FEV11..1
Number of clock periods +1
FEV0
0
FS Rising Edge between
Clock rising edge-X ns and
clock falling edge-X ns
Number of clock periods +1
1
Clock falling edge-X ns
and clock rising edge-X ns
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