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參數(shù)資料
| 型號： | Q67103-H6594 |
| 廠商： | SIEMENS AG |
| 英文描述： | Memory Time Switch Extended Large MTSXL |
| 中文描述： | 內存定時開關擴展大型MTSXL |
| 文件頁數(shù)： | 37/51頁 |
| 文件大?。?/td> | 1052K |
| 代理商： | Q67103-H6594 |
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PEB 2447
Detailed Register Description
Semiconductor Group
37
03.97
4.6
Access in demultiplexed
μ
P-interface mode:
Write, address:
Reset value:
Mask Register (MASK)
02
H
0F
H
A logical 1 disables the corresponding interrupt as described in ISTA from activating the
INT pin. A masked interrupt (bit set to
“1”) is stored internally and indicated, when reading
ISTA. It is also reset in this case.
4.7
Access in demultiplexed
μ
P-interface mode:
Read/write, address:
Reset value:
Memory Access Address/Code Register High (MACH)
04
H
0X
H
A write access (rising edge of WR or CS) to this register starts an indirect access to a
memory location.
MAC2..0
Memory Access Code
values to determine the type of access
to/from control and data memory locations. See
table 11
for all
possible code values.
Table 11
Memory Access Codes
MAC2
MAC1
MAC0
Function
Note: A write & read control memory command actually writes a specific CM location
and reads the same location in a second access.
MA10..8
Memory Address
(most significant) bits 10 to 8; refer to register
MAAL
Bit 7
Bit 0
0
0
0
0
FEC
PC
IR
PFI
Bit 7
Bit 0
MAC2
MAC1
MAC0
0
0
MA10
MA9
MA8
Max. Access Time
Clock Periods
–
4.5
6.5
4.5
8.5
0
0
0
0
1
All other combinations are not allowed
0
0
1
1
0
0
1
1
0
0
No operation
Write control memory
Write & read control memory
Read control memory
Read data memory
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