參數(shù)資料
型號: R2061K
英文描述: real-time clock ICs
中文描述: 實時時鐘IC
文件頁數(shù): 11/48頁
文件大?。?/td> 322K
代理商: R2061K
R2061 Series
12345
Rev.1.00 - 11 -
I
Register Settings
G
Control Register 1 (ADDRESS Eh)
D7
D6
WALE
DALE
D5
/12
24
D4
SCRA
TCH2
SCRA
TCH2
0
D3
TEST
D2
CT2
D1
CT1
D0
CT0
(For Writing)
WALE
DALE
/12
24
TEST
CT2
CT1
CT0
(For Reading)
0
0
0
0
0
0
0
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit
WALE,DALE
Description
0
Disabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers).
1
Enabling the alarm interrupt circuit (under the control of the settings of
the Alarm_W registers and the Alarm_D registers)
(Default)
(2) /12
24
/12-24-hour Mode Selection Bit
Description
Selecting the 12-hour mode with a.m. and p.m. indications.
Selecting the 24-hour mode
Setting the /12
24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
24-hour mode
12-hour mode
24-hour mode
00
12 (AM12)
12
01
01 (AM 1)
13
02
02 (AM 2)
14
03
03 (AM 3)
15
04
04 (AM 4)
16
05
05 (AM 5)
17
06
06 (AM 6)
18
07
07 (AM 7)
19
08
08 (AM 8)
20
09
09 (AM 9)
21
10
10 (AM10)
22
11
11 (AM11)
23
Setting the /12
24 bit should precede writing time data
(3) SCRATCH2
Scratch Bit 2
SCRATCH2
0
1
The SCRATCH2 bit is intended for scratching and accepts the reading and writing of 0 and 1.
The SCRATCH2 bit will be set to 0 when the PON bit is set to 1 in the Control Register 1.
(4) TEST
Test Bit
TEST
0
Normal operation mode.
1
Test mode.
The TEST bit is used only for testing in the factory and should normally be set to 0.
/12
24
0
1
(Default)
12-hour mode
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
Description
(Default)
Description
(Default)
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