參數(shù)資料
型號: R2061K
英文描述: real-time clock ICs
中文描述: 實時時鐘IC
文件頁數(shù): 9/48頁
文件大?。?/td> 322K
代理商: R2061K
R2061 Series
12345
Rev.1.00 - 9 -
G
Alarm Function
The R2061 incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at preset
times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers and the
Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of
multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and Sunday". The
Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from /INTR pin, and the Alarm_D
outputs also from /INTR pin. Each alarm function can be checked from the CPU by using a polling function.
G
High-precision Oscillation Adjustment Function
The R2061 has built-in oscillation stabilization capacitors (CG and CD), that can be connected to an external
crystal oscillator to configure an oscillation circuit. Two kinds of accuracy for this function are alternatives. To
correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is configured to allow
correction of a time count gain or loss (up to
±
1.5ppm or
±
0.5ppm at 25
°
C) from the CPU. The maximum range is
approximately
±
189ppm (or
±
63ppm) in increments of approximately 3ppm (or 1ppm). Such oscillation frequency
adjustment in each system has the following advantages:
* Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator with
a wide range of precision variations.
* Corrects seasonal frequency deviations through seasonal oscillation adjustment.
* Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC, through
oscillation adjustment in tune with temperature fluctuations.
G
Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function
The R2061 has 3 power supply pins (VCC, VSB, VDD), among them, VCC pin and VDD pin have monitoring
function of supply voltage. VCC power supply monitoring circuit makes /VDCC pin “L” when VCC power supply pin
becomes equal or lower than –VDET1. At the power-on of VDD, this circuit makes /VDCC pin turn off, or “H” after
the delay time, tDELAY from when the VCC power supply pin becomes equal or more than +VDET1.
The R2061 incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any
past oscillation halt, the oscillation halt sensing circuit, VDD monitoring flag, and power-on reset flag are useful for
judging the validity of time data.
Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the
fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery
backed-up.
The R2061 also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record
any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can be
selected between 2.1V and 1.35V through internal register settings. The sampling rate is normally 1s. The
oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the
supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply
voltage monitoring circuit can be applied to battery supply voltage monitoring.
G
Periodic Interrupt Function
The R2061 incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside from
interrupt signals generated by the alarm interrupt circuit for output from the /INTR pin. Periodic interrupt signals have
five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60 Hz (once per 1
minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals
also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1 Hz) and special form
adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The
condition of periodic interrupt signals can be monitored with using a polling function.
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