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參數(shù)資料
| 型號： | R2061K |
| 英文描述： | real-time clock ICs |
| 中文描述： | 實時時鐘IC |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 322K |
| 代理商： | R2061K |
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R2061 Series
12345
Rev.1.00 - 13 -
G
Control Register 2 (Address Fh)
D7
D6
VDSL
VDET
D5
/XST
D4
PON
D3
SCRA
TCH1
SCRA
TCH1
0
D2
CTFG
D1
WAFG
D0
DAFG
(For Writing)
VDSL
VDET
/XST
PON
CTFG
WAFG
DAFG
(For Reading)
0
0
Indefinite
1
0
0
0
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
Description
Selecting the VDD supply voltage monitoring threshold setting of 2.1v.
Selecting the VDD supply voltage monitoring threshold setting of 1.35v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
VDSL
0
1
(Default)
(2) VDET
Supply Voltage Monitoring Result Indication Bit
Description
Indicating supply voltage above the supply voltage monitoring threshold
settings.
Indicating supply voltage below the supply voltage monitoring threshold
settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage
monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
(3) /XST
Oscillation Halt Sensing Monitor Bit
/XST
Description
0
Sensing a halt of oscillation
1
Sensing a normal condition of oscillation
The /XST accepts the reading and writing of 0 and 1. The /XST bit will be set to 0 when the oscillation halt
sensing. The /XST bit will hold 0 even after the restart of oscillation.
(4) PON
Power-on-reset Flag Bit
PON
Description
0
Normal condition
1
Detecting VDD power-on -reset
The PON bit is for sensing power-on reset condition.
*
The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1
even after power-on.
*
When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, except /XST and PON. As a result, /INTR pin stops outputting.
*
The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
(5) SCRATCH1
Scratch Bit 1
SCRATCH1
Description
0
1
The SCRATCH1 bit is intended for scratching and accepts the reading and writing of 0 and 1. The
SCRATCH1 bit will be set to 0 when the PON bit is set to 1 in the Control Register 2.
VDET
0
(Default)
1
(Default)
(Default)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R2061K01-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2061K03-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2061S02-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2062 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2062K01-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
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